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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Wang, Zhengrong Liu, Christopher Beckmann, Nathan Nowatzki, Tony UCLA Los Angeles CA 90024 USA CMU Pittsburgh PA USA

ISBN: (纸本)9798400703294

To mitigate the data movement bottleneck on large multicore systems, the near-data computing paradigm (NDC) offloads computation to where the data resides on-chip. The benefit of NDC heavily depends on spatial affinity, where all relevant data are in the same location, e.g. same cache bank. However, existing NDC works lack a general and systematic solution: they either ignore the problem and abort NDC when there is no spatial affinity, or rely on error-prone manual data placement. Our insight is that the essential affinity relationship, i.e. data A should be close to data B, is orthogonal to microarchitecture details and input sizes. By co-optimizing the data structure and capturing this general affinity information in the data allocation interface, the allocator can automatically optimize for data affinity and load balance to make NDC computations truly near data. With this insight, we propose affinity alloc, a general framework to optimize data layout for near-data computing. It comprises an extended allocator runtime, co-optimized data structures, and lightweight extensions to the OS and microarchitecture. Evaluated on parallel workloads across broad domains, affinity alloc achieves 2.26x speedup and 1.76x energy efficiency over a state-of-the-art near-data computing technique with 72% traffic reduction.

关键词： near-data computing data Layout data Placement data Structure Co-Design Memory Allocation

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General, Flexible and Unified near-data computing

General, Flexible and Unified Near-Data Computing

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作者： Wang, Zhengrong University of California Los Angeles

学位级别：Ph.D., Doctor of Philosophy

Over the past decades, the memory hierarchy has increasingly become the bottleneck in general-purpose processors due to a widening gap between the growing demand for large data and the much slower scaling of conventional memory hierarchies. Therefore, conventional in-core computing suffers from increasingly expensive overheads such as excessive request messages, unnecessary data movement and coherence traffic, as well as limited off-chip band-width, to bring the data from memory to computing cores. To continue the performance and energy efficiency scaling, architects propose near-data computing (NDC) in which computations are offloaded to where the data is. However, existing NDC techniques fall short of providing generality and flexibility across different application domains, programming paradigms, computing substrates, which are crucial to the wide adoption of *** key insight is that the critical missing cornerstone for general and flexible near-data computing is a novel rich-semantic memory abstraction. Unlike existing byte-grained load/store operations, the new interface should express a wide range of rich semantics such as the access pattern, reuse distance, near-data computations, etc. Such high-level information is essential for the system to promptly recognize the program’s long-term behavior and adjust accordingly to reach optimal states. More importantly, the new interface should be as transparent as possible to programmers with automatic compiler analysis and runtime library support. Based on this, we can fundamentally revolutionize the memory interface and co-optimize computation and data *** dissertation explores a new ISA interface - streams - to precisely capture the program’s long-term memory and compute activities. Streams are incorporated into the program’s functional semantics and are exposed to the entire system stack to guide various policies. Our evaluation and analysis suggest serval key findings. First, a set of useful and preva

关键词： Cache optimization In-memory computing Memory hierarchy near-data computing Streams

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A 6.8TOPS/W Energy Efficiency, 1.5μW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for near-data computing with SSD

A 6.8TOPS/W Energy Efficiency, 1.5μW Power Consumption, Pul...

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14th IEEE Asian Solid-State Circuits Conference (A-SSCC)

作者： Tsurumi, Kota Suzuki, Kenta Takeuchi, Ken Chuo Univ Dept Elect Elect & Comnun Tokyo Japan

ISBN: (纸本)9781538664131

This paper proposes Pulse Width Modulation Neuromorphic (PWMNM) circuits, best suitable for near-data computing with SSD. The concept of neuromorphic computing is mimicking human brain with a number of mimicked-neurons of analog circuits. A mimicked-neuron in proposed PWMNM consists of 10 pairs of oscillators & clock counters, a micro controller and a charge pump. Proposed PWMNM achieves high energy efficiency of 6.8TOPS/W (Tera operations per second per Watt) and low power consumption of 1.5 mu W, thanks to matrix product operations are processed with number of output pulses as a function of the time instead of conventional current or voltage operation. Both proposed PWMNM and peripheral circuits of NAND flash memory are fabricated with a 180nm standard CMOS process and PWMNM can be embedded in SSD. Character recognition system is demonstrated by using proposed PWMNM, and the recognition accuracy of 93.3% is achieved.

关键词： Neuromorphic Pulse width modulation Oscillator Charge pump Low power consumption near-data computing

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Kobold: Simplified Cache Coherence for Cache-Attached Accelerators

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2023年第1期22卷 41-44页

作者： Brana, Jennifer Schwedock, Brian C. C. Manerkar, Yatin A. A. Beckmann, Nathan Univ Portland Pittsburgh PA 15213 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Michigan Ann Arbor MI 48104 USA

The ever-increasing cost of data movement in computer systems is driving a new era of data-centric computing. One of the most common data-centric paradigms is near-data computing (NDC), where accelerators are placed inside the memory hierarchy to avoid the costly transfer of data to the core. NDC systems show immense potential to improve performance and energy efficiency. Unfortunately, adding accelerators into the memory hierarchy incurs significant complexity for system integration because accelerators often require cache-coherent access to memory. The complex coherence protocols required to handle both cores and cache-attached accelerators result in significantly higher verification costs as well as an increase in directory state and on-chip network traffic. Furthermore, these mechanisms can cause cache pollution and worsen baseline processor performance. To simplify the integration of cache-attached accelerators, we present Kobold, a new coherence protocol and implementation which restricts the added complexity of an accelerator to its local tile. Kobold introduces a new directory structure within the L2 cache to track the accelerator's private cache and maintain coherence between the core and accelerator. A minor modification to the LLC protocol also enables accelerators to improve performance by bypassing the local L2. We verified Kobold's stable-state coherence protocols using the Murphi model checker and estimated area overhead using Cacti 7. Kobold simplifies integration of cache-attached accelerators, adds only 0.09% area over the baseline caches, and provides clear performance advantages versus naive extensions of existing directory coherence protocols.

关键词： Coherence Protocols Engines Complexity theory Multicore processing Costs Memory management Cache coherence data-centric near-data computing

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near-Stream computing: General and Transparent near-Cache Acceleration 28

Near-Stream Computing: General and Transparent Near-Cache Ac...

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28th Annual IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Wang, Zhengrong Weng, Jian Liu, Sihao Nowatzki, Tony Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781665420273

data movement and communication have become the primary bottlenecks in large multicore systems. The near-data computing paradigm provides a solution: move computation to where the data resides on-chip. Two challenges keep near-data computing from the mainstream: lack of programmer transparency and applicability. Programmer transparency requires providing sequential memory semantics with distributed computation, which requires burdensome coordination. Broad applicability requires support for combinations of address patterns (e.g. affine, indirect, multi-operand) and computation types (loads, stores, reductions, atomics). We find that streams - coarse grain memory access patterns - are a powerful ISA abstraction for near data offloading. Tracking data access at stream-granularity heavily reduces the burden of coordination for providing sequential semantics. Decomposing the problem using streams means that arbitrary combinations of address and computation patterns can be combined for broad generality. With this insight, we develop a paradigm called near-stream computing, comprising a compiler, CPU ISA extension, and a microarchitecture that facilitate programmer transparent computation offloading to shared caches. We evaluate our system on OpenMP kernels that stress broad addressing and compute behavior, and find that 46% of dynamic instructions can be offloaded to remote banks, reducing the network traffic by 76%. Overall it achieves 2.13x speedup over a state-of-the-art near-data computing technique, with a 1.90x energy efficiency gain.

关键词： Stream-Based ISAs Programmer-Transparent Acceleration near-data computing

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Sunder: Enabling Low-Overhead and Scalable near-data Pattern Matching Acceleration 21

Sunder: Enabling Low-Overhead and Scalable Near-Data Pattern...

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54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Sadredini, Elaheh Rahimi, Reza Imani, Mohsen Skadron, Kevin Univ Calif Riverside Riverside CA 92521 USA Univ Virginia Charlottesville VA USA Univ Calif Irvine Irvine CA USA

ISBN: (纸本)9781450385572

Automata processing is an efficient computation model for regular expressions and other forms of sophisticated pattern matching. The demand for high-throughput and real-time pattern matching in many applications, including network intrusion detection and spam filters, has motivated several in-memory architectures for automata processing. Existing in-memory architectures focus on accelerating the pattern-matching kernel, but either fail to support a practical reporting solution or optimistically assume that the reporting stage is not the performance bottleneck. However, gathering and processing the reports can be the major bottleneck, especially when the reporting frequency is high. Moreover, all the existing in-memory architectures work with a fixed processing rate (mostly 8-bit/cycle), and they do not adjust the input consumption rate based on the properties of the applications, which can lead to throughput and capacity loss. To address these issues, we present Sunder, an in-SRAM pattern matching architecture, to processes a reconfigurable number of nibbles (4-bit symbols) in parallel, instead of fixed-rate processing, by adopting an algorithm/architecture methodology to perform hardware-aware transformations. Inspired by prior work, we transform the commonly-used 8-bit processing to nibble-processing (4-bit processing) to reduce hardware requirements exponentially and achieve higher information density. This frees up space for storing reporting data in place, which significantly eliminates host communication and reporting overhead. Our proposed reporting architecture supports in-place report summarization and provides an easy access mechanism to read the reporting data. As a result, Sunder enables a low-overhead, high-performance, and flexible in-memory pattern-matching and reporting solution. Our results confirm that Sunder reporting architecture has zero performance overhead for 95% of the applications and incurs only 2% additional hardware overhead.

关键词： Automata processing hardware accelerator in-SRAM processing near-data computing pattern matching reconfigurable computing

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DynamAP: Architectural Support for Dynamic Graph Traversal on the Automata Processor

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2022年第4期19卷 60-60页

作者： Liu, Yiding Zhang, Xingyao Zhuang, Donglin Fu, Xin Song, Shuaiwen Univ Houston 4800 Calhoun Rd Houston TX 77004 USA Univ Sydney Sydney NSW 2006 Australia

Dynamic graph traversals (DGTs) currently are widely used in many important application domains, especially in this big-data era that urgently demands high-performance graph processing and analysis. Unlike static graph traversals, DGTs in real-world application scenarios require not only fast traversal acceleration itself but also, more importantly, a runtime strategy that can effectively accommodate the ever-evolving nature of the graph structure updates followed by a diverse range of graph traversal algorithms. Because of these special features, state-of-the-art designs on conventional compute-centric architectures (e.g., CPU and GPU) struggle to provide sufficient acceleration for DGT processing due to the dominating irregularmemory access patterns in graph traversal algorithms and inefficient platform-specific update mechanisms. In this article, we explore the algorithmic features and runtime requirements of real-world DGTs and identify their unique opportunities of acceleration on the recent Micron Automata Processor (AP), an in-situ memory-centric pattern-matching architecture. These features include the natural mapping between traversal algorithms' path exploration pattern to classic non-deterministic finite automata processing, AP's architectural and compilation support for DGTs' evolving traversal operations, and its inherent hardware fitness. However, despite these benefits, enabling highly efficient DGT execution on AP is non-trivial and faces several major challenges. To tackle them, we propose DynamAP, the first AP framework design that enables fast processing for general DGTs. DynamAP is oblivious to periodical traversal algorithm changes and can address the significant overhead caused by frequent graph updates and AP recompilation through our novel hybrid macro designs and associated efficient updating strategies. We evaluate DynamAP against the current DGT designs on a CPU, GPU, and AP with a range of widely adopted DGT algorithms and real-world grap

关键词： Accelerator system design FPGAs CGRAs and reconfigurable systems near-data computing systems designed around emerging/partially proven device technologies

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AQUOMAN: An Analytic-Query Offloading Machine 53

AQUOMAN: An Analytic-Query Offloading Machine

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53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Xu, Shuotao Bourgeat, Thomas Huang, Tianhao Kim, Hojun Lee, Sungjin Arvind MIT CSAIL Cambridge MA 02139 USA DGIST Daegu South Korea

ISBN: (纸本)9781728173832

Analytic workloads on terabyte data-sets are often run in the cloud, where application and storage servers are separate and connected via network. In order to saturate the storage bandwidth and to hide the long storage latency, such a solution requires an expensive server cluster with sufficient aggregate DRAM capacity and hardware threads. An alternative solution is to push the query computation into storage servers. In this paper we present an in-storage Analytics QUery Offloading MAchiNe (AQUOMAN) to "offload" most SQL operators, including multi-way joins, to SSDs. AQUOMAN executes Table Tasks, which apply a static dataflow graph of SQL operators to relational tables to produce an output table. Table Tasks use a streaming computation model, which allows AQUOMAN to process queries with a reasonable amount of DRAM for intermediate results. AQUOMAN is a general analytic query processor, which can be integrated in the database software stack transparently. We have built a prototype of AQUOMAN in FPGAs, and using TPC-H benchmarks on 1TB data sets, shown that a single instance of 1TB AQUOMAN disk, on average, can free up 70% CPU cycles and reduce DRAM usage by 60%. One way to visualize this saving is to think that if we run queries sequentially and ignore inter-query page cache reuse, MonetDB running on a 4-core, 16GB-DRAM machine with AQUOMAN augmented SSDs performs, on average, as well as a MonetDB running on a 32-core, 128GB-DRAM machine with standard SSDs.

关键词： Accelerator SQL analytics near-data computing FPGA Flash storage database

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RS-pCloud: A Peer-to-Peer Based Edge-Cloud System for Fast Remote Sensing Image Processing 13

RS-pCloud: A Peer-to-Peer Based Edge-Cloud System for Fast R...

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4th IEEE International Conference on Edge computing (IEEE EDGE) / IEEE World Congress on Services (SERVICES)

作者： Sun, Tongzheng Xiong, Jingpan Wang, Yang Meng, Tianhui Chen, Xi Xu, Chengzhong Chinese Acad Sci Shenzhen Inst Adv Technol Beijing Peoples R China Chinese Acad Sci Res Ctr Ecol & Environm Cent Asia Beijing Peoples R China Univ Macau Fac Sci & Technol Zhuhai Peoples R China

ISBN: (纸本)9781728182544

Modern remote sensing (RS) image application systems often distribute image processing tasks among multiple data centers and then gather the processed images from each center to efficiently synthesize the final product. In this paper, we exploit the edge-cloud architecture to design and implement a novel RS image service system, called RS-pCloud, which leverages the Peer-to-Peer (P2P) model to integrate multiple data centers and their associated edge networks. The data center as cloud platform is responsible for the storage and processing of original RS images, as well as the storage of partial processed images while the edge network is mainly for caching and sharing the processed images. With this design, RS-pCloud not only achieves the load sharing of processing works but also attains the data efficiency among the edges at the same time, which in turn improves the performance of the image processing and reduce the cost of the data transmission as well. RS-pCloud is designed to be used in a transparent way where it receives a query task from the user through a certain cloud platform, split the task into different sub-tasks, according to the location of the data they required, and then distribute the sub-tasks to corresponding clouds for near-data processing, the returned results from each cloud are first cached in specific edge for further sharing and then gathered at the client to synthesize the final product. We implemented and deployed RS-pCloud on three clusters in conjunction with an edge network to show its performance advantages over traditional single-cluster systems.

关键词： remote sensing image edge-cloud architecture Peer-to-Peer near-data computing load sharing

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Collective Affinity Aware Computation Mapping 20

Collective Affinity Aware Computation Mapping

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ACM International Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Kandemir, Mahmut T. Ryoo, Jihyun Zhao, Hui Jung, Myoungsoo Karakoy, Mustafa Penn State Univ University Pk PA 16802 USA Univ North Texas Denton TX 76203 USA Korea Adv Inst Sci & Technol Daejeon South Korea TUBITAK BILGEM Gebze Turkey

ISBN: (纸本)9781450380751

This work defines the concept of collective affinity. It is claimed that collective affinity has more potential than single core-centric affinity, for data locality optimization in manycores. The reason is that collective affinity captures the potential benefits of transferring computations originally assigned to one core to other cores. Next, building upon the collective affinity concept and a cache content estimation strategy, it presents a computation-to-core mapping strategy, specifically tuned for exploiting near data computing by reducing distance-to-data.

关键词： Optimizing Compilers near-data computing Manycores

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