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near-memory computing: Past, present, and future

MICROPROCESSORS AND MICROSYSTEMS 2019年 71卷 102868-000页

作者： Singh, Gagandeep Chelini, Lorenzo Corda, Stefano Awan, Ahsan Javed Stuijk, Sander Jordans, Roel Corporaal, Henk Boonstra, Albert-Jan Eindhoven Univ Technol Dept Elect Engn Eindhoven Netherlands Ericsson Res Dept Cloud Syst & Platforms Kista Sweden ASTRON Netherlands Inst Radio Astron R&D Dept Dwingeloo Netherlands

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory called near-memory computing (NMC) more viable. Processing right at the "home" of data can significantly diminish the data movement problem of dataintensive applications. In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC. (C) 2019 Elsevier B.V. All rights reserved.

关键词： near-memory computing Data-centric computing Modeling Computer architecture Application characterization Survey

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A Review of near-memory computing Architectures: Opportunities and Challenges 21

A Review of Near-Memory Computing Architectures: Opportuniti...

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21st Euromicro Conference on Digital System Design (DSD)

作者： Singh, Gagandeep Chelini, Lorenzo Corda, Stefano Awan, Ahsan Javed Stuijk, Sander Jordans, Roel Corporaal, Henk Boonstra, Albert-Jan Eindhoven Univ Technol Dept Elect Engn Eindhoven Netherlands Imperial Coll London Dept Comp London England ASTRON Netherlands Inst Radio Astron R&D Dept Dwingeloo Netherlands

ISBN: (纸本)9781538673768

The conventional approach of moving stored data to the CPU for computation has become a major performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in integration technologies have made the decade-old concept of coupling compute units close to the memory (called near-memory computing) more viable. Processing right at the home of data can completely diminish the data movement problem of data-intensive applications. This paper focuses on analyzing and organizing the extensive body of literature on near-memory computing across various dimensions: starting from the memory level where this paradigm is applied, to the granularity of the application that could be executed on the near-memory units. We highlight the challenges as well as the critical need of evaluation methodologies that can be employed in designing these special architectures. Using a case study, we present our methodology and also identify topics for future research to unlock the full potential of near-memory computing.

关键词： near-memory computing data centric computing modeling of computer architecture application characterization survey

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Concurrent Data Structures for near-memory computing 17

Concurrent Data Structures for Near-Memory Computing

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29th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)

作者： Liu, Zhiyu Calciu, Irina Herlihy, Maurice Mutlu, Onur Brown Univ Comp Sci Dept Providence RI 02912 USA VMware Res Grp Palo Alto CA USA Swiss Fed Inst Technol Comp Sci Dept Zurich Switzerland

ISBN: (纸本)9781450345934

The performance gap between memory and CPU has grown exponentially. To bridge this gap, hardware architects have proposed near-memory computing (also called processing-in-memory, or PIM), where a lightweight processor (called a PIM core) is located close to memory. Due to its proximity to memory, a memory access from a PIM core is much faster than that from a CPU core. New advances in 3D integration and die-stacked memory make PIM viable in the near future. Prior work has shown significant performance improvements by using PIM for embarrassingly parallel and data-intensive applications, as well as for pointer-chasing traversals in sequential data structures. However, current server machines have hundreds of cores, and algorithms for concurrent data structures exploit these cores to achieve high throughput and scalability, with significant benefits over sequential data structures. Thus, it is important to examine how PIM performs with respect to modern concurrent data structures and understand how concurrent data structures can be developed to take advantage of PIM. This is paper is the first to examine the design of concurrent data structures for PIM. We show two main results: (1) naive PIM data structures cannot outperform state-of-the-art concurrent data structures, such as pointer-chasing data structures and FIFO queues, (2) novel designs for PIM data structures, using techniques such as combining, partitioning and pipelining, can outperform traditional concurrent data structures, with a significantly simpler design.

关键词： concurrent data structures parallel programs processing-in-memory near-memory computing

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A Survey of MRAM-Centric computing: From near memory to In memory

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computing 2023年第2期11卷 318-330页

作者： Li, Yueting Bai, Tianshuo Xu, Xinyi Zhang, Yundong Wu, Bi Cai, Hao Pan, Biao Zhao, Weisheng Beihang Univ Sch Integrated Circuit Sci & Engn Beijing Beijing10019 Peoples R China Beihang Univ Fert Beijing Inst Beijing 100191 Peoples R China Beihang Univ MIIT Key Lab Spintron Beijing 100191 Peoples R China Vimicro Corp Natl Key Lab Digital Multimedia Chip Technol Beijing 100191 Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 210095 Peoples R China Southeast Univ Natl ASIC Syst Engn Ctr Nanjing 211189 Peoples R China

Conventional von Neumann architecture suffers from bottlenecks in computing performance and power consumption due to frequent data exchange between memory and processing units. To overcome this issue, research on novel computing architectures including near-memory computing (NMC) and in-memory computing (IMC) has been accelerated based on emerging nonvolatile memory devices. Among various potential candidates, spintronic-based magnetic random-access memory (MRAM) has come into a research and development hotspot by its ultralow switching energy, nonvolatility, and superior endurance. This paper outlines the background, trends, and challenges involved in the development of MRAM-centric computing, and highlights the recent prototypes and advances in applications based on MRAM-NMC and MRAM-IMC.

关键词： Random access memory Magnetic tunneling Arrays Approximate computing memory architecture Magnetic separation Optimization near-memory computing in-memory computing MRAM neural network hybrid memory architecture

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Toward Efficient System-on-Module for Design-Space Exploration of Analog Spiking Neural Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第8期71卷 3538-3549页

作者： El-Masry, Moamen Werner, Thilo Zjajo, Amir Weigel, Robert Infineon Technol AG D-85579 Neubiberg Germany Friedrich Alexander Univ Erlangen Nuremberg Inst Elect Engn D-91054 Erlangen Germany Ferroelect Memory Co GmbH D-01099 Dresden Germany Innatera Nanosyst BV NL-2289 EX Rijswijk Netherlands

In this paper, we present an integrated system-on-module for design-space exploration of neurosynaptic behavior in non-volatile memory enhanced spiking neural networks. The system operates in locally-analog, globally-digital modus, facilitating the exploration and validation of both, individual computational components, and the characteristic spike-based features of neurosynaptic arrays. The key advantage of the system lies in its reconfigurable, adaptable, and interchangeable components, which enable precise and reproducible firing patterns. By leveraging these capabilities, various aspects of neurosynaptic behavior can be examined and manipulated. To enhance the weight retention mechanism, the platform incorporates embedded resistive-RAM, ensuring the preservation of synaptic weights. This integration further supports the accurate representation and processing of synaptic information. Experimental results in 28 nm CMOS technology demonstrate the feasibility and effectiveness of the proposed methodology in characterizing spiking neural network components.

关键词： Nonvolatile memory Random access memory Reliability Artificial intelligence Resistance Neurons Synapses Brain-inspired computing neuromorphic VLSI design spiking neural networks system-on-module non-volatile memory resistive-RAM near-memory computing

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Sparsity-Oriented MRAM-Centric computing for Efficient Neural Network Inference

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computing 2024年第1期12卷 97-108页

作者： Cui, Jia-Le Guo, Yanan Chen, Juntong Liu, Bo Cai, Hao Southeast Univ Sch Elect Sci & Engn Nanjing 210000 Peoples R China

near-memory computing (NMC) and in- memory computing (IMC) paradigms show great importance in non-von Neumann architecture. Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a promising candidate to realize both NMC and IMC for resource-constrained applications. In this work, two MRAM-centric computing frameworks are proposed: triple-skipping NMC (TS-NMC) and analog-multi-bit-sparsity IMC (AMS-IMC). The TS-NMC exploits the sparsity of activations and weights to implement a write-read-calculation triple skipping computing scheme by utilizing a sparse flag generator. The AMS-IMC with reconfigured computing bit-cell and flag generator accommodate bit-level activation sparsity in the computing. STT-MRAM array and its peripheral circuits are implemented with an industrial 28-nm CMOS design-kit and an MTJ compact model. The triple-skipping scheme can reduce memory access energy consumption by 51.5x when processing zero vectors, compared to processing non-zero vectors. The energy efficiency of AMS-IMC is improved by 5.9x and 1.5x (with 75% input sparsity) as compared to the conventional NMC framework and existing analog IMC framework. Verification results show that TS-NMC and AMS-IMC achieved 98.6% and 97.5% inference accuracy in MNIST classification, with energy consumption of 14.2 nJ/pattern and 12.7 nJ/pattern, respectively.

关键词： In-memory computing near-memory computing neural network STT-MRAM sparsity vector and matrix

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Advanced Integration-Inspired Process-in-memory: A Comprehensive Review of Design, Challenges, and Future Prospects

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IEEE ACCESS 2024年 12卷 160957-160972页

作者： Cheng, Jinhui Guan, Zhaoliang Fu, Jiangduo Xu, Hangyu Ke, Jinkun State Grid Smart Grid Res Inst Co Ltd State Key Lab Adv Power Transmiss Technol Beijing 102209 Peoples R China

This work provides a comprehensive overview of advanced integration-inspired memory process design, focusing on the integration methods of 2D, 2.5D, and 3D. The integration of compute and memory blocks has demonstrated encouraging outcomes in enhancing memory access latency and energy efficiency for data-centric operations. The challenges and future prospects for PIM design include addressing trade-offs in the integration process, thermal management in highly integrated 3D designs, developing design automation tools for 3D designs, and identifying practical application scenarios for PIM to maximize its benefits. The use of through-silicon vias (TSVs) technology enables the efficient design of 3D structures with improved bandwidth density, while hybrid bonding technology shows advantages in achieving higher interconnect density and data transmission bandwidth. Monolithic integration represents a distinctive solution for high-density module integration, whereby custom circuit layers are stacked vertically in a single chip. This approach represents an efficient alternative to traditional 2D integration technologies. These advances in integration technology provide a roadmap for the future of PIM design and its application in real-world scenarios. In conclusion, the continuous development and integration of different technologies in PIM design has the potential to significantly enhance performance, energy efficiency, and integration density for data-centric tasks.

关键词： Computer architecture memory management Three-dimensional displays Logic Microprocessors Bandwidth Data communication Artificial intelligence SRAM cells Energy efficiency Process-in-memory heterogeneous integration near-memory computing

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A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2023年第7期58卷 2109-2124页

作者： Sehgal, Rishabh Thareja, Tanmay Xie, Shanshan Ni, Can Kulkarni, Jaydeep P. Univ Texas Austin Chandra Family Dept Elect & Comp Engn Austin TX 78712 USA Intel Corp Austin TX 78746 USA Apple Inc San Diego CA 92121 USA

major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) that contribute to similar to 15% area and similar to 50% energy of the overall macro and are susceptible to non-linearities, leakage, and process variations, which causes deep neural network (DNN) inference/training accuracy loss. As DNN models increase in size, the number of DACs steps required per inference increases exponentially. This work proposes a four-pronged approach to address the challenges in CIM designs: 1) binary-weighted-bitline-precharge scheme utilizing dedicated reference voltages to perform input bit-serial multiplication in the charge domain, eliminating the need for dedicated DAC circuits;2) leakage-tolerant, input-dependent-bitline-keeper circuits that maintain the local-bitline voltages;3) hybrid-charge-sharing-based integrating-ADCs to improve the ADC conversion time by leveraging the reference voltages, thereby improving ADC latency while achieving a compact ADC design;and 4) efficient data movement and utilization of analog-to-digital co-computation. Fabricated in TSMC 65 nm, the experimental results for the compute-in-static-RAM (CISRAM) silicon prototype show an average macro energy efficiency of 153-2453.76 TOPs/W. The average macro energy efficiency is 2.3x more than the latest state of the art mentioned in the comparison table.

关键词： Common Information Model (computing) Random access memory Sensors SRAM cells memory management Deep learning Neural networks Artificial intelligence (AI) binary precharge compute-in-memory (CIM) digital-to-analog converter (DAC)-less CIM hardware (HW) accelerator inference in-memory computing near-memory computing static RAM (SRAM)

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Overflow-free Compute Memories for Edge AI Acceleration

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ACM TRANSACTIONS ON EMBEDDED computing SYSTEMS 2023年第5期22卷 1-23页

作者： Ponzina, Flavio Rios, Marco Levisse, Alexandre Ansaloni, Giovanni Atienza, David Ecole Polytech Fed Lausanne EPFL STI IEM Embedded Syst Lab ELG 130 Stn 11 CH-1015 Lausanne Switzerland

Compute memories are memory arrays augmented with dedicated logic to support arithmetic. They support the efficient execution of data-centric computing patterns, such as those characterizing Artificial Intelligence (AI) algorithms. These architectures can provide computing capabilities as part of the memory array structures (In-memory computing, IMC) or at their immediate periphery (near-memory computing, NMC). By bringing the processing elements inside (or very close to) storage, compute memories minimize the cost of data access. Moreover, highly parallel (and, hence, high-performance) computations are enabled by exploiting the regular structure of memory arrays. However, the regular layout of memory elements also constrains the data range of inputs and outputs, since the bitwidths of operands and results stored at each address cannot be freely varied. Addressing this challenge, we herein propose a HW/SW co-design methodology combining careful per-layer quantization and inter-layer scaling with lightweight hardware support for overflow-free computation of dot-vector operations. We demonstrate their use to implement the convolutional and fully connected layers of AI models. We embody our strategy in two implementations, based on IMC and NMC, respectively. Experimental results highlight that an area overhead of only 10.5% (for IMC) and 12.9% (for NMC) is required when interfacing with a 2KB subarray. Furthermore, inferences on benchmark CNNs show negligible accuracy degradation due to quantization for equivalent floating-point implementations.

关键词： In-memory computing near-memory computing edge machine learning quantization convolutional neural networks

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Accelerating Large-Scale Graph-Based nearest Neighbor Search on a Computational Storage Platform

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IEEE TRANSACTIONS ON COMPUTERS 2023年第1期72卷 278-290页

作者： Kim, Ji-Hoon Park, Yeo-Reum Do, Jaeyoung Ji, Soo-Young Kim, Joo-Young Korea Adv Inst Sci & Technol Dept Elect Engn Daejeon South Korea Amazon Alexa AI Seattle WA 98108 USA Samsung Elect Adv Solut Team Memory Business Gyonggi Do South Korea Korea Adv Inst Sci & Technol Dept Elect Engn Daejeon South Korea

k-neighbor search is one of the fundamental tasks in various applications and the hierarchical navigable small world (HNSW) has recently drawn attention in large-scale cloud services, as it easily scales up the database while offering fast search. On the other hand, a computational storage device (CSD) that combines programmable logic and storage modules on a single board becomes popular to address the data bandwidth bottleneck of modern computing systems. In this paper, we propose a computational storage platform that can accelerate a large-scale graph-based nearest neighbor search algorithm based on SmartSSD CSD. To this end, we modify the algorithm more amenable on the hardware and implement two types of accelerators using HLS-and RTL-based methodology with various optimization methods. In addition, we scale up the proposed platform to have 4 SmartSSDs and apply graph parallelism to boost the system performance further. As a result, the proposed computational storage platform achieves 75.59 query per second throughput for the SIFT1B dataset at 258.66W power dissipation, which is 12.83x and 17.91x faster and 10.43x and 24.33x more energy efficient than the conventional CPU-based and GPU-based server platform, respectively. With multi-terabyte storage and custom acceleration capability, we believe that the proposed computational storage platform is a promising solution for cost-sensitive cloud datacenters.

关键词： ANN search architecture cloud data-center FPGA in-storage computing near-memory computing SmartSSD

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