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near-memory computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第1期16卷 1-32页

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Adapt Dynam Syst Nothnitzer Str 46 D-01062 Dresden Germany German Univ Cairo Elect Dept Cairo 11835 Egypt Tech Univ Darmstadt Merckstr 25 D-64283 Darmstadt Germany

The near-memory computing (NMC) paradigm has transpired as a promising method for overcoming the memory wall challenges of future computing architectures. Modern systems integrating 3D-stacked DRAM memory can be leveraged to prevent unnecessary data movement between the main memory and the CPU. FPGA vendors have started introducing 3D memories to their products in an effort to remain competitive on bandwidth requirements of modern memory-intensive applications. Recent NMC proposals target various types of data processing workloads such as graph processing, MapReduce, sorting, machine learning, and database analytics. In this article, we conduct a literature survey on previous proposals of NMC systems on FPGAs integrated with 3D memories. By leveraging the high bandwidth offered from such memories together with specifically designed hardware, FPGA architectures have become a competitor to GPU solutions in terms of speed and energy efficiency. Various FPGA-based NMC designs have been proposed with software and hardware optimization methods to achieve high performance and energy efficiency. Our review investigates various aspects of NMC designs such as platforms, architectures, workloads, and tools. We identify the key challenges and open issues with future research directions.

关键词： near-memory computing 3D stacking FPGA architectures high-bandwidth memory

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HNMC: Hybrid near-memory computing Circuit for Neural Network Acceleration

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第11期71卷 4763-4767页

作者： Liu, Xiyan Liu, Qiang Tianjin Univ Sch Microelect Tianjin Key Lab Imaging & Sensing Microelect Techn Tianjin 300072 Peoples R China

The state-of-the-art lookup table (LUT)-based solution usually requires large-size memory which hampers the implementation of a high speed and small area computing scheme. To minimize the area while achieving a fast speed, this brief presents a hybrid near-memory computing (HNMC) circuit with a new LUT reduction technique to accelerate the LUT-based multiplication in neural network. Experimental results show that compared to the 4-bit multipliers based on pure LUT, pure logic and near-memory computing (NMC) circuits, the multiplier based on HNMC reduces up to 75% delay, 81% area and 80% power consumption;the 8-bit convolution engine based on HNMC increases throughput by 2x and reduces area up to 77% and power consumption up to 40% compared to the state-of-the-art NMC convolution engine.

关键词： Circuits Table lookup Delays Random access memory Optimization Xenon Neural networks near-memory computing SRAM look-up table multiplier neural networks

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HeNCoG: A Heterogeneous near-memory computing Architecture for Energy Efficient GCN Acceleration

HeNCoG: A Heterogeneous Near-memory Computing Architecture f...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Hwang, Seung-Eon Song, Duyeong Park, Jongsun Korea Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9798350330991;9798350331004

Graph convolutional network (GCN), which first applies convolutional operations to process graph data, has gained attention in various tasks involving relational data. Previous GCN accelerators have been designed with heterogeneous cores, considering two stages of inference (aggregation and combination), or with a unified core based on the inference of multi layer as an iterative sparse-dense matrix multiplication. However, those prior works have suffered from an unnecessary large number of multiply-accumulate (MAC) operations and/or main memory accesses. In this paper, we propose HeNCoG, a GCN accelerator that utilizes a heterogeneous MAC array core for the combination stage and a near-memory computing core for the aggregation stage. In HeNCoG, considering that the number of MAC operations is significantly reduced when changing the stage execution order, the combination stage is executed first with a row-stationary dataflow. In the aggregation stage, magneto-resistive random-access memory (MRAM)-based near-memory computing is employed to reduce the number of main memory accesses needed to access the adjacency matrix in the graph dataset. Graph partitioning and double buffering techniques are also applied to further improve hardware efficiencies. Simulation results show that the HeNCoG architecture reduces execution cycles by 97% and memory accesses by 42% compared to previous works.

关键词： Graph Convolutional Network Sparse Matrix Multiplication near-memory computing Domain Specific Accelerator

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STT-MRAM-based near-memory computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency 24

STT-MRAM-based Near-Memory Computing Architecture with Read ...

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29th ACM / IEEE International Symposium on Low Power Electronics and Design (ISLPED)

作者： Jang, Yunho Kim, Yeseul Park, Jongsun Korea Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9798400706882

Spin transfer torque magnetic random access memory (STT-MRAM)-based near-memory computing (NMC) architecture has been actively studied due to its potential for high-throughput and energy-efficient processing of AI algorithms. However, the low read bandwidth of STT-MRAM limits improvements in throughput of NMC architecture by failing to provide enough data to digital logic located near memory arrays. In this paper, we propose reference voltage recycling read scheme (RRS) and hybrid stationary dataflow scheme (HDS) to address the low read bandwidth issue in STT-MRAM. The proposed RRS allows for the recycling of previously developed reference bit-line voltage in a memory array during sequential read operations, enhancing read bandwidth as well as energy-efficiency of STT-MRAM. In addition, HDS balances the demand for input and weight data in digital logics located near memory arrays, facilitating full utilization of digital logics despite the limited read bandwidth of STT-MRAM. As a result, this approach can improve throughput of NMC architecture. The simulations using a 28nm CMOS process show that the proposed STT-MRAM-based NMC architecture can achieve TOPS/W of 8.45 and TOPS/mm(2) of 1.37 with 8-bit input and weight, regardless of the data patterns.

关键词： STT-MRAM near-memory computing Read scheme Dataflow

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Compiler-Assisted Kernel Selection for FPGA-based near-memory computing Platforms 31

Compiler-Assisted Kernel Selection for FPGA-based Near-Memor...

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31st IEEE Annual International Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany German Univ Cairo Elect Dept IES Lab Cairo Egypt Tech Univ Darmstadt Darmstadt Germany Ctr Scalable Data Analyt & Artificial Intelligenc Leipzig Germany

ISBN: (纸本)9798350312058

The speed of modern computing systems has improved significantly, thanks to advances in CMOS technology. However, the memory bandwidth of DRAM has not kept pace with these improvements in terms of latency and energy consumption, which is known as the memory wall [1]. FPGAs with high-bandwidth memory (HBM) provide significantly improved performance on memory-intensive tasks, such as graph processing and machine learning. By leveraging 3D-stacked DRAM memory on FPGAs, it is possible to realize the near-memory computing (NMC) paradigm, which involves offloading some kernels to be processed close to the memory. While there have been many studies on NMC accelerators, there is no established method for determining which application kernels are suitable for execution near the HBM. To fully realize the potential of FPGA-HBM architectures, it is important to identify offloading candidates without relying on programmers' knowledge. However, this is a non-trivial task due to the complexity of modern applications. To address this issue, we propose a compiler-assisted tool-flow for the automatic selection of kernels to be offloaded. © 2023 IEEE.

关键词： characterization High-bandwidth memory near-memory computing parallel architectures prediction

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Design and implementation of near-memory computing array architecture based on shared buffer

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High Technology Letters 2022年第4期28卷 345-353页

作者： SHAN Rui GAO Xu FENG Yani HUI Chao CUI Xinyue CHAI Miaomiao School of Electronic Engineering Xi’an University of Posts and TelecommunicationsXi’an 710121P.R.China School of Computer Xi’an University of Posts and TelecommunicationsXi’an 710121P.R.China

Deep learning algorithms have been widely used in computer vision,natural language processing and other ***,due to the ever-increasing scale of the deep learning model,the requirements for storage and computing performance are getting higher and higher,and the processors based on the von Neumann architecture have gradually exposed significant shortcomings such as consumption and long *** order to alleviate this problem,large-scale processing systems are shifting from a traditional computing-centric model to a data-centric model.A near-memory computing array architecture based on the shared buffer is proposed in this paper to improve system performance,which supports instructions with the characteristics of store-calculation integration,reducing the data movement between the processor and main *** data reuse,the processing speed of the algorithm is further *** proposed architecture is verified and tested through the parallel realization of the convolutional neural network(CNN)*** experimental results show that at the frequency of 110 MHz,the calculation speed of a single convolution operation is increased by 66.64%on average compared with the CNN architecture that performs parallel calculations on field programmable gate array(FPGA).The processing speed of the whole convolution layer is improved by 8.81%compared with the reconfigurable array processor that does not support near-memory computing.

关键词： near-memory computing shared buffer reconfigurable array processor convolutional neural network(CNN)

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Leakage Reuse for Energy Efficient near-memory computing of Heterogeneous DNN Accelerators

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2021年第4期11卷 762-775页

作者： Hossain, Md Shazzad Savidis, Ioannis Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA

The exploration of custom deep neural network (DNN) accelerators for highly energy constrained edge devices with on-device intelligence is gaining traction in the research community. Despite the superior throughput and performance of custom accelerators as compared to CPUs or GPUs, the energy efficiency and versatility of state-of-the-art DNN accelerators is constrained due to a) the storage and movement of a large volume of data and b) the limited scope of monolithic architectures, where the entire accelerator executes only a single model at any given time. In this paper, a multi-voltage domain heterogeneous DNN accelerator is proposed that executes multiple models simultaneously with different power-performance operating points. The proposed architecture concurrently implements near-memory computing and leakage reuse, where the leakage current of idle memory banks within each processing element is utilized to deliver current to the adjacently placed multiply-and-accumulate (MAC) units. The proposed architecture and circuit techniques are evaluated with SPICE simulation in a 65 nm CMOS technology. The simulation results indicate that the proposed heterogeneous architecture with leakage reuse results in an energy efficiency of 3.27 tera-operations per second per watt (TOPS/W) as compared to a conventional monolithic and single voltage domain architecture that exhibits an energy efficiency of 0.0458 TOPS/W. In addition, the proposed accelerator that implements the leakage reuse technique on only half of the memory elements storing the weights reduces the power consumption of the sub-arrays of processing elements by 26% (99.4 mW) as compared to an accelerator that does not apply leakage reuse.

关键词： System-on-chip Random access memory memory management Computer architecture Leakage currents Computational modeling Receivers Leakage reuse near-memory computing on-chip SRAM heterogeneous DNN accelerator ubiquitous DNN applications edge devices

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Evaluation of Power-of-two Quantization for Multiplier-less near-memory and In-memory computing Schemes for Biomedical Applications 9

Evaluation of Power-of-two Quantization for Multiplier-less ...

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9th IEEE Nordic Circuits and Systems Conference (NorCAS)

作者： Gautier, Antoine Larras, Benoit Martens, Olev John, Deepu Frappe, Antoine Univ Polytech Hauts France Univ Lille CNRS IEMNUMR 8520Cent Lille Lille France Tallinn Univ Technol Inst Elect Tallinn Estonia Univ Coll Dublin Dublin Ireland

ISBN: (纸本)9798350337570

Embedded Artificial Intelligence and Artificial Neural Networks and their implementation at the edge, as close as possible to the sensors, is an opportunity to develop biomedical applications such as long-term monitoring or point-of-care devices, but the implementation of such networks is constrained by hardware limitations: battery life and power consumption as well as silicon area. This paper focuses on the hardware implementation cost of a neuron/perceptron. Two different solutions that respond to the challenge of reducing the hardware cost of embedded artificial intelligence neural networks and neurons are studied. The first solution studied is the replacement of multipliers by shifters allowed by the use of non-uniform powers-of-two quantization of the network weights, which is validated on three different classification cases (arrhythmia, sleep-apnea and image recognition). The second solution studied is a comparative study of the advantages and limitations of conventional von-Neumann and in/near-memory implementation of a neuron in terms of hardware implementation cost. Performance metrics are estimated in 28nm FDSOI technology.

关键词： artificial neural networks log quantization in-memory computing near-memory computing multiplier-less arrhythmia detection sleep-apnea detection

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DEA-NIMC: Dynamic Energy-Aware Policy for near/In-memory computing Hybrid Architecture 36

DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Com...

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36th IEEE International System-on-Chip Conference (SOCC)

作者： Wu, Yu-Cheng Huang, Chi-Tse Wu, An-Yeu (Andy) Natl Taiwan Univ Dept Elect Engn Taipei Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan

ISBN: (纸本)9798350300116

In-memory computing (IMC) has become the current trend to accelerate the inference of deep neural networks (DNNs). Nonetheless, IMC suffers from variations that significantly degrade the inference accuracy, while near-memory computing (NMC) maintains the ideal accuracy but at the expense of energy efficiency. In this work, we leverage the NMC/IMC hybrid architecture and propose a dynamic energy-aware policy to strike a better trade-off between accuracy and energy efficiency. Our approach takes advantage of deep reinforcement learning (DRL) to dynamically allocate workloads between NMC and IMC at the data level. Furthermore, we consider the varying energy overhead of NMC usage across different DNN layers. Compared with the prior works, we enhance the accuracy by up to 8.8% on CIFAR-10 and 4.6% on CIFAR-100 while consuming the same amount of energy.

关键词： In-memory computing near-memory computing hybrid computing deep reinforcement learning

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A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical near-memory computing

ADVANCED INTELLIGENT SYSTEMS

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ADVANCED INTELLIGENT SYSTEMS 2020年第9期2卷

作者： In, Jae Hyun Kim, Young Seok Song, Hanchan Kim, Gwang Min An, Jangho Jeon, Jae Bum Kim, Kyung Min KAIST Adv Inst Sci & Technol KAIST Dept Mat Sci & Engn 291 Daehak Ro Daejeon 34141 South Korea

Memristive stateful logic allows complete in-memory computing and is considered to be a next-generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near-memory error correction method for a typical bipolar-type memristor stateful logic system is proposed. An error correction principles using a HfO2-based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one-bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.

关键词： error corrections memristors near-memory computing resistive switching memories stateful logics

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