Multimedia communication, with its strong requirements for high speed, assured quality, and reliable networking, is stimulating a great research effort towards the development of real-time protocols. Some protocols of...
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ISBN:
(纸本)0444814817
Multimedia communication, with its strong requirements for high speed, assured quality, and reliable networking, is stimulating a great research effort towards the development of real-time protocols. Some protocols of this type have been proposed, which offer communication services with different levels of commitment in providing quality of service guarantees. In this paper we study the feasibility of an extended client interface that allows more flexibility in the client-network interactions. The proposed model improves the utilisation of network resources, and increases the network's capability to support multimedia traffic, while continuing to offer a guaranteed quality of service.
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic reallocation of bandwidth. It is desi...
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ISBN:
(纸本)044482023X
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic reallocation of bandwidth. It is designed to support real-time multimedia applications and high-speed computer communication. DTM uses a novel medium-access technique and provides a multicast connection-oriented service. In this paper, the connection establishment in the DTM network is discussed and a scheme for fast connection establishment is presented. The scheme allows for fast set-up of channels which results in an efficient usage of the network's bandwidth and a short access delay for the user. Buffer handling and memory management implementations at a host interface supporting this scheme are also presented.
Two new service disciplines in an ATM Multiplexer or a Multiplexer based ATM switch for connectionless services are presented. Their main advantage is to avoid or minimize a fragmentation process that a frame undergoe...
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ISBN:
(纸本)0444815120
Two new service disciplines in an ATM Multiplexer or a Multiplexer based ATM switch for connectionless services are presented. Their main advantage is to avoid or minimize a fragmentation process that a frame undergoes when applying commonly used ATM Multiplexing disciplines. This is especially important when the data sources are applications running on Local Area networks and generating frames, and the Multiplexer is an access unit in the BISDN ATM based Public network used for a public LAN -WAN -LAN interconnection service. The disciplines proposed offer several advantages, namely they facilitate the reassembling of cells into frames and offer an overall better frame error rate performance, if similar strategies are carried out throughout the ATM network, when the network is lossy in terms of cells, and the cell loss tends to occur in bursts, as it is the case when by overloading, some buffers overflow. This is particularly likely to happen when the ATM network is operated not in connection oriented mode, or when resource allocation cannot be done effectively due to the impossibility to know in advance the bandwidth requirements of the connectionless sources, and where, as the case will be, one wants to obtain statistical gains in the network. This paper presents the new disciplines, simulate the performance against other disciplines already proposed for ATM Multiplexers, and compares their performance and the complexity for their hardware implementation.
System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are aff...
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System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are affected by the limitation of sub nanometer technologies that cannot be shrunk further. network on Chip (NoC) is a scalable communication system that can provide efficient solutions for on-chip interconnection problems of SoCs such as re-configurability for multiple embedded applications. Most of the reconfigurable NoCs presented in the past improve performance of SoC at the expense of higher power and additional hardware. In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power requirements of the system for different SoC applications. The proposed NoC architecture can also be considered as a hard IP for future partially configurable FPGA devices. Simulation and experimental results of our approach are compared with the recent on-chip interconnection approaches that supports our claim.
This paper provides a short description of thirteen computer network simulators that are mainly used for educational purposes. Criteria for the evaluation and comparison of the simulators were presented. The criteria ...
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This paper provides a short description of thirteen computer network simulators that are mainly used for educational purposes. Criteria for the evaluation and comparison of the simulators were presented. The criteria are applied in order to compare the simulators being described. This comparative analysis is useful when selecting a suitable simulator for teaching a specific computer networks course.
The increased application of wireless technologies including Wireless Sensor Actuator networks (WSAN) in industry has given rise to a plethora of protocol designs. These designs target metrics ranging from energy effi...
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The increased application of wireless technologies including Wireless Sensor Actuator networks (WSAN) in industry has given rise to a plethora of protocol designs. These designs target metrics ranging from energy efficiency to real-time constraints. Protocol design typically starts with a requirements specification, and continues with analytic and model-based simulation analysis. State-of- the-art network simulators provide extensive physical environment emulation, but still have limitations due to model abstractions. Deployment testing on actual hardware is therefore vital in order to validate implementability and usability in the real environment. The contribution of this article is a deployment testing of the Dual-Mode Adaptive MAC (DMAMAC) protocol. DMAMAC is an energy efficient protocol recently proposed for real-time process control applications and is based on Time Division Multiple Access (TDMA) in conjunction with dual-mode operation. A main challenge in implementing DMAMAC is the use of a dynamic superframe structure. We have successfully implemented the protocol on the Zolertia Z1 platform using TinyOS (2x). Our scenario- based evaluation shows minimal packet loss and smooth mode-switch operation, thus indicating a reliable implementation of the DMAMAC protocol.
QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. A single QPACE node is based on the IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus net...
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QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. A single QPACE node is based on the IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The compute power of the processor is provided by 8 Synergistic Processing Units. Making effcient use of these accelerator cores in scientific applications is challenging. In this paper we describe our strategies for porting applications to the QPACE architecture and report on performance numbers.
Over the years, the Internet has become a field in which a small number of large Internet companies dominate most of the Internet services. As users get used to using their services, the users' generated content a...
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Over the years, the Internet has become a field in which a small number of large Internet companies dominate most of the Internet services. As users get used to using their services, the users' generated content and the data about their online behaviors are concentrated in such companies. This phenomenon, called "data consolidation", has become a serious problem, which makes the Internet society seek to decentralize the current Internet. The decentralized Internet aims to (i) prevent the concentration of user data in a few giant companies like Google and Facebook, and (ii) give users full ownership and control of their data. Various technical solutions that address the data consolidation problem have been proposed;however, those solutions focus on somewhat different scopes of the problem often from their limited viewpoints. The main contributions in this paper are the following. First, we survey the solutions relevant to Internet decentralization based on the following criteria: data consolidation, data ownership, and the privacy of user data. Second, we suggest a holistic reference framework from a functional viewpoint, while the prior proposals in the literature handle a limited set of requirements. Last, we seek to identify remaining research issues, considering additional requirements that have not been addressed in the existing solutions.
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