Finding good puncturing patterns for rate-compatible non-binary ldpc codes are considered over additive white Gaussian noise (AWGN) channels in this paper. We first study several popular puncturing schemes for binary ...
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ISBN:
(纸本)9781457703218
Finding good puncturing patterns for rate-compatible non-binary ldpc codes are considered over additive white Gaussian noise (AWGN) channels in this paper. We first study several popular puncturing schemes for binaryldpccodes and generalize them to non-binary ldpc codes, where the effects of short cycles in Tanner graph are rarely investigated. By carefully studying the impacts of short cycles when puncturing, we put forward a novel puncturing scheme for rate-compatible non-binary ldpc codes. Simulation results show that the proposed puncturing scheme is superior to the above known ones for rate-compatible non-binary ldpc codes over AWGN channels at certain cases.
non-binary ldpc codes offer higher performances than their binary counterpart but suffer from highest decoding complexity. A solution to reduce the decoding complexity is the use of stochastic decoding algorithm, but ...
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ISBN:
(纸本)9781457701016
non-binary ldpc codes offer higher performances than their binary counterpart but suffer from highest decoding complexity. A solution to reduce the decoding complexity is the use of stochastic decoding algorithm, but the computational complexity of probability generation in the first step is very high. In this paper, we propose a simple method to fast generate the probability especially in high-order modulation schemes. Simulation results show that the proposed algorithm causes negligible performance degradation with reduction in computational complexity for stochastic decoding of non-binary ldpc codes, which gives some advantages in hardware implementation of the decoders.
This paper presents a cycle-based rate-compatible puncturing technique for non-binary (NB) low-density parity-check (ldpc) codes. The proposed puncturing technique is based on the connectivity of the short non-binary ...
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ISBN:
(纸本)9781509017461
This paper presents a cycle-based rate-compatible puncturing technique for non-binary (NB) low-density parity-check (ldpc) codes. The proposed puncturing technique is based on the connectivity of the short non-binary (NB) cycles present in the Tanner graph. The connectivity of a cycle is measured by the extrinsic message degree (EMD). The short cycles with low values of EMD degrade the performance of iterative decoders significantly. The proposed technique selects the variable nodes for puncturing by reckoning their involvements in the short NB cycles with a low EMD. Simulations in different contexts are performed to check the efficiency of the proposed technique.
The traditional majority-logic decoding (MLgD) based algorithms suffer error-floors for decoding non-binary ldpc codes with small column weights. This paper presents a bit-reliability based MLgD (BRB-MLgD) algorithm w...
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ISBN:
(纸本)9781467364324
The traditional majority-logic decoding (MLgD) based algorithms suffer error-floors for decoding non-binary ldpc codes with small column weights. This paper presents a bit-reliability based MLgD (BRB-MLgD) algorithm with low error-floors for non-binary ldpc codes. The proposed algorithm is carried out based on the binary representations of nonbinary symbols. The reliability update along each edge of the Tanner graph of a non-binaryldpc code is in terms of bits rather than symbols. Thus, its computational complexity and memory consumption are less than those of the existing MLgD based algorithms. Simulation results indicate that the proposed algorithm can significantly reduce error-floors with small performance degradation in the waterfall region.
This paper presents a novel truncation rule for the extended min-sum (EMS) decoding of non-binary low-density parity-check (NB-ldpc) codes. The conventional NB-ldpc decoders involve vector-messages of length equal to ...
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ISBN:
(纸本)9781538638217
This paper presents a novel truncation rule for the extended min-sum (EMS) decoding of non-binary low-density parity-check (NB-ldpc) codes. The conventional NB-ldpc decoders involve vector-messages of length equal to the field size q. The complexity of these decoders increases significantly as q increases. In the EMS algorithm, the vector-messages are truncated by discarding the less-likely symbols. In this paper, we propose a truncation rule so that the lengths of the vector-messages are reduced to the so-far best limit without compromising on the error correction capability. We devise a proximity matrix which helps to identify the essential components of a vector-message for truncation. The proposed truncation rule has been applied to several NB-ldpccodes of different field sizes. Simulation results for these codes show that the proposed rule can achieve the maximum truncation with negligible performance loss.
This paper reduces the complexity of decoding non-binary low-density parity-check (ldpc) codes by set partition. In the check node update, the input vectors are partitioned into several sets such that different elemen...
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ISBN:
(纸本)9781509018062
This paper reduces the complexity of decoding non-binary low-density parity-check (ldpc) codes by set partition. In the check node update, the input vectors are partitioned into several sets such that different elements in the virtual matrix enjoy various computational strategies. As a result, the proposed algorithm achieves high computational efficiency by setting strategies according to the correct probability of these elements. Simulation results indicate that it significantly decreases the complexity of check node update with negligible performance loss.
For decoding non-binary low-density parity-check (ldpc) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not...
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ISBN:
(纸本)9781457705397
For decoding non-binary low-density parity-check (ldpc) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worse, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.
This paper presents a majority-logic decoding (MLgD) algorithm for non-binary ldpc codes based on a novel expansion of the Tanner graph. The expansion introduced converts the Q-ary graph into a binary one, which makes...
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ISBN:
(纸本)9781538669006
This paper presents a majority-logic decoding (MLgD) algorithm for non-binary ldpc codes based on a novel expansion of the Tanner graph. The expansion introduced converts the Q-ary graph into a binary one, which makes the new MLgD algorithm more attractive for hardware implementations. Proposed algorithm performs significantly better than the existing MLgD algorithms in the waterfall region, and it shows a much lower error-floor as well. Algorithm only requires integer additions, comparisons, finite field operations and some binary operations. Thus, it offers an effective trade-off between performance and complexity in decoding non-binary ldpc codes.
In this paper, an overview of recent achievements in the design and decoding of non-binary low-density paritycheck (ldpc) codes is provided. non-binary constructions based on ultra-sparse matrices are compared with bi...
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ISBN:
(纸本)9781424468331
In this paper, an overview of recent achievements in the design and decoding of non-binary low-density paritycheck (ldpc) codes is provided. non-binary constructions based on ultra-sparse matrices are compared with binary low-density parity-check codes and turbo codes from satellite communication standards, to show that larger coding gains ( outperforming the binary competitors by at least 0.3 dB) can be achieved on the AWGN channel, especially in the moderate/short block regimes. Thanks to this excellent performance, non-binary ldpc codes represent an appealing solution for space communications. Index Terms-Belief propagation, non-binary ldpc codes, space communications, satellite communications.
In this paper we analyze the performance of several bit-interleaving strategies applied to non-binary Low-Density Parity-Check (ldpc) codes over the Rayleigh fading channel. The technique of bit-interleaving used over...
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ISBN:
(纸本)9781467304375;9781467304368
In this paper we analyze the performance of several bit-interleaving strategies applied to non-binary Low-Density Parity-Check (ldpc) codes over the Rayleigh fading channel. The technique of bit-interleaving used over fading channel introduces diversity which could provide important gains in terms of frame error probability and detection. This paper demonstrates the importance of the way of implementing the bit-interleaving, and proposes a design of an optimized bit-interleaver inspired from the Progressive Edge Growth algorithm. This optimization algorithm depends on the topological structure of a given ldpc code and can also be applied to any degree distribution and code realization. In particular, we focus on non-binary ldpc codes based on graph with constant symbol-node connection d(v) = 2. These regular (2, dc)-NB-ldpccodes demonstrate best performance, thanks to their large girths and improved decoding thresholds growing with the order of Finite Field. Simulations show excellent results of the proposed interleaving technique compared to the random interleaver as well as to the system without interleaver.
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