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A modified non-binary LDPC scheme based on watermark symbols in high speed optical transmission systems

OPTICS COMMUNICATIONS 2016年 365卷 49-53页

作者： Wang, Liming Qiao, Yaojun Yu, Qian Zhang, Wenbo Beijing Univ Posts & Telecommun Sch Informat & Commun Engn State Key Lab Informat Photon & Opt Commun Beijing 100876 Peoples R China Beijing Univ Posts & Telecommun Sch Sci Beijing 100876 Peoples R China

We introduce a watermark non-binary low-density parity check code (NB-LDPC) scheme, which can estimate the time-varying noise variance by using prior information of watermark symbols, to improve the performance of NB-LDPC codes. And compared with the prior-art counterpart, the watermark scheme can bring about 0.25 dB improvement in net coding gain (NCG) at bit error rate (BER) of le-6 and 36.8-81% reduction of the iteration numbers. Obviously, the proposed scheme shows great potential in terms of error correction performance and decoding efficiency. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Optical communications non-binary low density parity check codes Bit error rate performance Decoding efficiency

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Variable-Length Coding With Shared Incremental Redundancy: Design Methods and Examples

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IEEE TRANSACTIONS ON COMMUNICATIONS 2019年第9期67卷 5981-5995页

作者： Wang, Haobo Ranganathan, Sudarsan V. S. Wesel, Richard D. SK Hynix Memory Solut Amer Inc San Jose CA 95134 USA MIT IDSS Cambridge MA 02142 USA Univ Calif Los Angeles Dept Elect & Comp Engn Los Angeles CA 90095 USA

Variable-length (VL) coding with feedback is a commonly used technique that can approach point-to-point Shannon channel capacity with a significantly shorter average codeword length than fixed-length coding without feedback. This paper uses the inter-frame coding of Zeineddine and Mansour, originally introduced to address varying channel-state conditions in broadcast wireless communication, to approach capacity on point-to-point channels using VL codes without feedback. The per-symbol complexity is comparable to decoding the VL code with feedback (plus the additional complexity of a small peeling decoder amortized over many VL codes) and presents the opportunity for encoders and decoders that utilize massive parallel processing, where each VL decoder can process simultaneously. This paper provides an analytical framework and a design process for the degree distribution of the inter-frame code that allows the feedback-free system to achieve 96% or more of the throughput of the original VL code with feedback. As examples of VL codes, we consider non-binary (NB) low-density parity-check (LDPC), binary LDPC, and convolutional VL codes. The NB-LDPC VL code with an 8-bit CRC and an average codeword length of 336 bits achieves 85% of capacity with four rounds of ACK/NACK feedback. The proposed scheme using shared incremental redundancy without feedback achieves 97% of that performance or 83% of the channel capacity.

关键词： Forward error correction incremental redundancy feedback channel capacity broadcast point-to-point low density parity check codes non-binary low density parity check codes convolutional codes variable-length coding hybrid ARQ

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FPGA Implementation Scheme of Mixed Logarithmic domain FFT-BP Decoding Algorithm Based on non-binary LDPC codes 37

FPGA Implementation Scheme of Mixed Logarithmic domain FFT-B...

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37th Chinese Control Conference (CCC)

作者： Wang, Ziyong Meng, Jiahui Deng, Zhibin Zhang, Liang Gao, Jingpeng Wuhan Maritime Commun Res Inst Wuhan 430000 Hubei Peoples R China Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Heilongjiang Peoples R China

ISBN: (纸本)9789881563958

In this paper, an improved decoding algorithm for non-binary low density parity check (NB-LDPC) codes with low decoding complexity and suitable for field-programmable gate array (FPGA) implementation is proposed, which is a mixed logarithmic domain FFT-BP decoding algorithm (Mixed Log-FFT-BP) for the problem of high complexity of the existing decoding algorithms for non-binary LDPC codes. The algorithm combines the traditional Log-BP algorithm with the FFT-BP algorithm, and simplifies the update of the check nodes in the iterative decoding process. A large number of convolution operations are converted into multiplication operations in frequency domain by using FFT transform and IFFT transform. The multiplication of the original FFT-BP algorithm is converted into the addition and look-up table operations in the logarithmic domain. Then, the logarithm of the probability information is directly solved, so that it can be decoded in the logarithmic domain, which saves the computation of the log likelihood ratio, and then reduces the complexity. Simulation results show that under the additive Gauss white noise channel, when the bit error rate is 10(-5), compared with BP algorithm, Log-BP algorithm and FFT-BP algorithm, the performance of Mixed Log-FFT-BP algorithm is not decreased, and all of them remain within the range of 0.1-0.2dB.

关键词： non-binary low density parity check codes Mixed Log-FFT-BP decoding Field-programmable gate array Complexity

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A low-Complexity Adaptive Extended Min-Sum Algorithm for non-binary LDPC codes 5

A Low-Complexity Adaptive Extended Min-Sum Algorithm for Non...

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5th International Conference on Computational Intelligence and Applications (ICCIA)

作者： Kim, Min-Ho Park, Kyeong-Bin Chung, Ki-Seok Hanyang Univ Dept Elect & Comp Engn Seoul South Korea

ISBN: (纸本)9781728160429

The extended min-sum algorithm (EMS) for decoding non-binary low density parity check (NB-LDPC) codes reduces the decoding complexity by truncating the message vector by retaining only the most reliable symbols. However, the EMS algorithm does not consider that the noise of the received codeword is gradually reduced as the iteration count goes up. In this paper, we propose a low-complexity adaptive EMS algorithm, called threshold-based EMS (TB-EMS). The TB-EMS algorithm has a simple adaptive rule to calculate the new message vector length compared to the A-EMS. The proposed algorithm selects one of two message vector lengths. Experimental results show that the proposed algorithm reduces the decoding complexity with minimal performance degradation compared with the EMS algorithm. Further, the decoding performance of the TB-EMS is better than A-EMS.

关键词： non-binary low density parity check codes Extended Min-Sum algorithm low-complexity decoding Message truncation rule

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An Improved Decoding Algorithm Based on Min-max for NB-LDPC codes 36

An Improved Decoding Algorithm Based on Min-max for NB-LDPC ...

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第36届中国控制会议

作者： Mengzhu Chen Jin Xu Jun Xu Danfeng Zhao Jiahui Meng Wireless Technology preresearch Team ZTE Corporation College of Information and Communication Engineering Harbin Engineering University

ISBN: (纸本)9781538629185

When the code length is moderate,non-binary low-density parity-check（NB-LDPC） codes can achieve better error correcting performance than their binary counterparts at the expense of higher decoding *** check node processing is a major bottleneck of NB-LDPC *** this paper,Min-max decoding algorithm is proposed based on a new forward backward processing method of check nodes,select only a part of the most reliable information to the forward-backward calculation process,and change the variable nodes to check nodes（v-to-c） generation of *** this algorithm,a kind of code（768,1152） defined on GF（4） is simulated and compared with belief propagation in log domain（LOG-BP） decoding *** results show Min-max decoding algorithm reduce information storage requirements and the computational complexity,conducive to engineering implementation.

关键词： non-binary low density parity check codes Min-max decoding algorithm check nodes

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Efficient Search Path Reduction for NB-LDPC codes with T-EMS Algorithm 15

Efficient Search Path Reduction for NB-LDPC Codes with T-EMS...

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15th IEEE International Conference on ASIC, ASICON 2023

作者： Quan, Xuewei Ji, Houren You, Xiaohu Zhang, Chuan Nanjing China Purple Mountain Laboratories Nanjing China

ISBN: (纸本)9798350312980

In comparison to the forward-backward update of extended min-sum (EMS) algorithm, the trellis EMS (T-EMS) algorithm for non-binary low density parity check codes (NB-LDPC) introduces an extra trellis column during check nodes (CNs) updates, significantly enhancing parallelism and facilitating hardware implementation. However, in high-order or high code rate scenarios, the T-EMS algorithm exhibits considerable latency caused by excessive configurations searching for the largest reliability selection. To address this, the paper propose an enhanced algorithm, named as path reduction T-EMS (RT-EMS) algorithm, to simplify the configuration space through applying an additional filtering to the elements in each column of the trellis, retaining only the elements that are deemed more trustworthy from the column's perspective. Moreover, a data compensation strategy is also proposed to tackle the data scarcity issues for some syndrome values in the extra trellis column. Finally, the simulation results demonstrate that RT-EMS algorithm can achieve more than 50% complexity reduction with a negligible performance degradation. © 2023 IEEE.

关键词： complexity reduction non-binary low density parity check codes search space trellis extended min-sum

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FPGA Implementation Scheme of Mixed Logarithmic domain FFT-BP Decoding Algorithm Based on non-binary LDPC codes

FPGA Implementation Scheme of Mixed Logarithmic domain FFT-B...

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第37届中国控制会议

作者： Ziyong Wang Jiahui Meng Zhibin Deng Liang Zhang Jingpeng Gao Wuhan Maritime Communications Research Institute College of Information and Communication Engineering Harbin Engineering University

In this paper,an improved decoding algorithm for non-binary low density parity check（NB-LDPC） codes with low decoding complexity and suitable for field-programmable gate array（FPGA） implementation is proposed,which is a mixed logarithmic domain FFT-BP decoding algorithm（Mixed Log-FFT-BP） for the problem of high complexity of the existing decoding algorithms for non-binary LDPC *** algorithm combines the traditional Log-BP algorithm with the FFT-BP algorithm,and simplifies the update of the check nodes in the iterative decoding process.A large number of convolution operations are converted into multiplication operations in frequency domain by using FFT transform and IFFT *** multiplication of the original FFT-BP algorithm is converted into the addition and look-up table operations in the logarithmic ***,the logarithm of the probability information is directly solved,so that it can be decoded in the logarithmic domain,which saves the computation of the log likelihood ratio,and then reduces the *** results show that under the additive Gauss white noise channel,when the bit error rate is 10,compared with BP algorithm,Log-BP algorithm and FFT-BP algorithm,the performance of Mixed Log-FFT-BP algorithm is not decreased,and all of them remain within the range of 0.1-0.2 dB.

关键词： non-binary low density parity check codes Mixed Log-FFT-BP decoding Field-programmable gate array Complexity

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