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11th International Conference on Graphics and Image Processing (ICGIP)

作者： Jiang, Peng Dou, Zheng Harbin Engn Univ Harbin Peoples R China

ISBN: (纸本)9781510635241

Low-density parity-check code (LDPC) is a kind of better error correction code which is played an important role in the reliability transmission of communication systems. In the aspect of decoding algorithm, the NMS algorithm becomes the mainstream algorithm dues to its lower complexity. what's more, the Semi-serial decoding algorithm was put forward to reduce decoding iterations. However, the compensation factor of NMS algorithm is a fixed value and the Semi-serial decoding algorithm only considers one aspect of reducing iterations. In the actual decoding process, this value varies with the degree of the check node and the number of iterations. in order to solve the problems of these algorithms, this paper will propose a new improved algorithm. Firstly, we will adopt a dynamic compensation factor to improve performance of NMS algorithm on regular LDPC code. Then combined with the idea of Semi-serial decoding algorithm to reduce the number of iterations. The dynamic factor is firstly analyzed theoretically by density evolution theory. Then through the Monte Carlo experiment and the true LLR, the suitable dynamic compensation factors can be obtained which is changes with the number of iterations.

关键词： LDPC Compensation factor normalized min-sum algorithm Semi-serial decoding algorithm

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Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第6期71卷 2897-2910页

作者： Jang, Boseon Jang, Hyejung Kim, Sungho Choi, Kangjoon Park, In-Cheol Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea

The 5G New-Radio (NR) communication standard requires high throughput and low latency, so low-density parity-check (LDPC) codes, which have higher inherent parallelism and lower decoding complexity than turbo codes, were adopted as the main coding method for data channels. In traditional LDPC min-sum decoders, the check node unit was realized using a sorting unit based on the min-tree structure. However, this structure resulted in high hardware complexity and long latency. To address this issue, we propose a new sorting method based on the thermometer code-based number system. Additionally, we introduce a new LDPC decoding architecture that reduces the number of QSN stages from two to one, significantly lowering the shifting logic complexity needed to support different lifting sizes. This is achieved by using relative shift amounts instead of absolute shift amounts specified in the parity check matrix. The proposed decoder implemented using a partially parallel structure in a 65nm CMOS technology satisfies the various operation modes and the throughput requirements of the 5G NR standard, and boasts a higher normalized throughput than state-of-the-art LDPC decoders.

关键词： Low-density parity-check codes thermometer code normalized min-sum algorithm VLSI hardware implementation 5G new-radio standard area-efficient quasi-cyclic LDPC decoder

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Adaptive deactivation and zero-forcing scheme for low-complexity LDPC decoders

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EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING 2017年第1期2017卷 1页

作者： Kim, Taehyun Baik, Jonghyun Lee, Myeongwoo Heo, Jun Korea Univ Sch Elect Engn 145 Anam Ro Seoul 02841 South Korea LG Elect 19Yangjae Daero 11 Gil Seoul 06772 South Korea Samsung Elect 1-1 Samsungjeonja Ro Hwaseong Si 18448 South Korea

A modified message propagation algorithm is proposed for a low-complexity decoder of low-density parity-check (LDPC) codes, which controls the information propagated from variable and check nodes. The proposed threshold-based node deactivation for variable nodes and zero-forcing scheme for check nodes remarkably reduce decoding complexity required for similar error performance. In the proposed scheme, different thresholds, which are determined from the base matrix of the LDPC codes, are applied for each type of variable node. In addition, thresholds for deactivating variable nodes are increased while the decoding process is operated for a reduction in decoding complexity without early error floor, which is a drawback of the conventional threshold-based deactivation scheme. Simulation results show that the proposed scheme enables normalized min-sum decoders to decode successfully with less complexity than the conventional threshold-based deactivating scheme.

关键词： Low-density parity-check codes Protograph-based extrinsic transfer chart normalized min-sum algorithm Complexity reduction

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Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2011年第1期58卷 98-111页

作者： Chen, Xiaoheng Kang, Jingyu Lin, Shu Akella, Venkatesh Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10(-12) and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board.

关键词： Alignment field programmable logic array (FPGA) folding low-density parity-check (LDPC) decoder memory system optimization normalized min-sum algorithm quasi-cyclic low-density parity-check (QC-LDPC) codes very large scale integration (VLSI) implementation

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Simplified 2-Dimensional Scaled min-sum algorithm for LDPC Decoder

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2017年第3期12卷 1262-1270页

作者： Cho, Keol Lee, Wang-Heon Chung, Ki-Seok Hanyang Univ Dept Elect Engn Seoul South Korea Hanyang Univ Dept Elect & Comp Engn Seoul South Korea Hansei Univ Dept IT Gunpo Si Gyeonggi Do South Korea

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

关键词： Error-correction code Low-density parity-check code LDPC decoder min-sum algorithm normalized min-sum algorithm

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An Area Time-Efficient Structure to Find the Approximate First Two minima for min-sum-Based LDPC Decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2016年第8期63卷 793-797页

作者： Zhu, Xi He, Guanghui Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China

Aiming at reducing the hardware complexity of low-density parity-check (LDPC) decoders based on min-sum algorithms, this brief presents a general structure to find the minimum value and an approximate second minimum value. The proposed structure is proved to obtain the exact second minimum value with high probability in theory, and simulation results demonstrate that only a negligible degradation of error performance is introduced when adopting the proposed structure in LDPC decoders. Furthermore, mixed radix architecture is investigated to improve the area-time efficiency. Implemented in a SMIC 65-nm CMOS technology, the proposed architecture significantly improves the overall area-time efficiency compared with state-of-the-art works.

关键词： Approximate first two minimum values generator low-density parity-check (LDPC) decoder normalized min-sum algorithm

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Efficient Memory Optimization And High Throughput Decoding Architecture Based on LDPC Codes

Efficient Memory Optimization And High Throughput Decoding A...

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International Conference on Information Communication and Embedded Systems (ICICES)

作者： Ngangom, Leevaston Manikandan, V Vel Tech Multitech Dr Rangaragan Dr Sakunthala En Madras Tamil Nadu India

ISBN: (纸本)9781467357869;9781467357876

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. Here, the memory bandwidth is the key performance limiting factor. And the decoding throughput of a LDPC decoder is limited by this memory bandwidth requirement. The decoder implementation complexity has been the bottleneck of its application. This paper present a specific optimization called vectorization to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasicyclic LDPC codes. It is shown that this presented hardware structure will be highly competent in high throughput and low decoding latency applications.

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