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Adaptive discrete cosine transform-based image compression method on a heterogeneous system platform using open computing language

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JOURNAL OF ELECTRONIC IMAGING 2014年第6期23卷

作者： Alqudami, Nasser Kim, Shin-Dug Yonsei Univ Coll Engn Dept Comp Sci Seoul 120749 South Korea

Discrete cosine transform (DCT) is one of the major operations in image compression standards and it requires intensive and complex computations. Recent computer systems and handheld devices are equipped with high computing capability devices such as a general-purpose graphics processing unit (GPGPU) in addition to the traditional multicores CPU. We develop an optimized parallel implementation of the forward DCT algorithm for the JPEG image compression using the recently proposed open computing language (openCL). This openCL parallel implementation combines a multicore CPU and a GPGPU in a single solution to perform DCT computations in an efficient manner by applying certain optimization techniques to enhance the kernel execution time and data movements. A separate optimal openCL kernel code was developed (CPU-based and GPU-based kernels) based on certain appropriate device-based optimization factors, such as thread-mapping, thread granularity, vector-based memory access, and the given workload. The performance of DCT is evaluated on a heterogeneous environment and our openCL parallel implementation results in speeding up the execution of the DCT by the factors of 3.68 and 5.58 for different image sizes and formats in terms of workload allocations and data transfer mechanisms. The obtained speedup indicates the scalability of the DCT performance. (C) 2014 SPIE and IS&T

关键词： forward discrete cosine transform image compression heterogeneous computing open computing language

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Hardware and software architectures for computationally efficient three-dimensional ultrasonic data compression

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IET CIRCUITS DEVICES & SYSTEMS 2016年第1期10卷 54-61页

作者： Govindan, Pramod Wang, Boyang Ravi, Prashaanth Saniie, Jafar IIT Dept Elect & Comp Engn Chicago IL 60616 USA

Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for real-time ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using open computing language (openCL) targeted on Nvidia GT 750M graphical processing unit. openCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

关键词： volumetric data hardware architecture ultrasonic imaging Xilinx Zynq data compression medical imaging application system-on-chip software architecture industrial application discrete wavelet transform realtime ultrasonic imaging application graphical processing unit SoC hardware platform graphics processing units three-dimensional ultrasonic data compression reconfigurable ultrasonic system-on-chip data storage 3D ultrasonic data compression algorithm open computing language openCL discrete wavelet transforms ultrasound technology Nvidia GT 750M

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Scalable and massively parallel Monte Carlo photon transport simulations for heterogeneous computing platforms

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JOURNAL OF BIOMEDICAL OPTICS 2018年第1期23卷 1-4页

作者： Yu, Leiming Nina-Paravecino, Fanny Kaeli, David Fang, Qianqian Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Northeastern Univ Dept Bioengn Boston MA 02115 USA

We present a highly scalable Monte Carlo (MC) three-dimensional photon transport simulation platform designed for heterogeneous computing systems. Through the development of a massively parallel MC algorithm using the open computing language framework, this research extends our existing graphics processing unit (GPU)-accelerated MC technique to a highly scalable vendor-independent heterogeneous computing environment, achieving significantly improved performance and software portability. A number of parallel computing techniques are investigated to achieve portable performance over a wide range of computing hardware. Furthermore, multiple thread-level and device-level load-balancing strategies are developed to obtain efficient simulations using multiple central processing units and GPUs. (c) The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License.

关键词： Monte Carlo open computing language heterogeneous computing photon transport

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Comparison of High Level FPGA Hardware Design for Solving Tri-Diagonal Linear Systems

Comparison of High Level FPGA Hardware Design for Solving Tr...

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14th Annual International Conference on Computational Science

作者： Warne, David J. Kelson, Neil A. Hayward, Ross F. Queensland Univ Technol Brisbane Qld 4001 Australia Queensland Univ Technol High Performance Comp & Res Support Brisbane Qld Australia Queensland Univ Technol Sch Elect Engn & Comp Sci Brisbane Qld Australia

Reconfigurable computing devices can increase the performance of compute intensive algorithms by implementing application specific co-processor architectures. The power cost for this performance gain is often an order of magnitude less than that of modern CPUs and GPUs. Exploiting the potential of reconfigurable devices such as Field-Programmable Gate Arrays (FPGAs) is typically a complex and tedious hardware engineering task. Recently the major FPGA vendors (Altera, and Xilinx) have released their own high-level design tools, which have great potential for rapid development of FPGA based custom accelerators. In this paper, we will evaluate Altera's openCL Software Development Kit, and Xilinx's Vivado High Level Sythesis tool. These tools will be compared for their performance, logic utilisation, and ease of development for the test case of a tri-diagonal linear system solver.

关键词： Reconfigurable computing Field Programmable Gate Arrays High Level Synthesis open computing language Numerical Linear Algebra Tri-diagonal Linear Systems

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Performance Characterization of the NAS Parallel Benchmarks in openCL

Performance Characterization of the NAS Parallel Benchmarks ...

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IEEE International Symposium on Workload Characterization (IISWC)

作者： Seo, Sangmin Jo, Gangwon Lee, Jaejin Seoul Natl Univ Sch Comp Sci & Engn Ctr Manycore Programming Seoul 151744 South Korea

ISBN: (纸本)9781457720642

Heterogeneous parallel computing platforms, which are composed of different processors (e.g., CPUs, GPUs, FPGAs, and DSPs), are widening their user base in all computing domains. With this trend, parallel programming models need to achieve portability across different processors as well as high performance with reasonable programming effort. openCL (open computing language) is an open standard and emerging parallel programming model to write parallel applications for such heterogeneous platforms. In this paper, we characterize the performance of an openCL implementation of the NAS Parallel Benchmark suite (NPB) on a heterogeneous parallel platform that consists of general-purpose CPUs and a GPU. We believe that understanding the performance characteristics of conventional workloads, such as the NPB, with an emerging programming model (i.e., openCL) is important for developers and researchers to adopt the programming model. We also compare the performance of the NPB in openCL to that of the openMP version. We describe the process of implementing the NPB in openCL and optimizations applied in our implementation. Experimental results and analysis show that the openCL version has different characteristics from the openMP version on multicore CPUs and exhibits different performance characteristics depending on different openCL compute devices. The results also indicate that the application needs to be rewritten or re-optimized for better performance on a different compute device although openCL provides source-code portability.

关键词： CPU Computational modeling DSP FPGA GPU Graphics processing unit Indexes Kernel Multicore processing NAS Parallel Benchmark suite NAS parallel benchmarks NPB open computing language openCL Optimization graphics processing units heterogeneous parallel comp

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Performance Analysis of Fast Fourier Transform on Field Programmable Gate Arrays and Graphic Cards 1

Performance Analysis of Fast Fourier Transform on Field Prog...

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International Conference on computing, Electronic and Electrical Engineering (ICE Cube)

作者： Ibrahim, Muhammad Khan, Omar Natl Univ Comp & Emerging Sci Dept Elect Engn Peshawar Pakistan Natl Univ Comp & Emerging Sci Dept Comp Sci Peshawar Pakistan

ISBN: (纸本)9781509012527

The Fast Fourier Transform (FFT) is an important algorithm in the fields of science and engineering, where it is used in diverse areas such as communications, signal processing, instrumentation, image and video analysis, etc. The algorithm is essentially a fast implementation of the Discrete Fourier Transform which allows it to reduce the asymptotic complexity of the latter from O(n(2)) to the former's O(n log n). In this paper, the radix-2 decimation in time FFT algorithm is implemented and investigated on Field Programmable Gate Arrays (FPGA) and Graphic Processing Units (GPU). The hardware descriptive language Verilog HDL (VHDL) is used for the FPGA, while the open computing language (openCL) is used for the GPU. Both implementations are compared with various pre-installed IP-core modules of Xilinx and MATLAB for complex input of various sample sizes. From the results, it is concluded that the FPGA shows faster performance for a large number of FFT's of small sizes. On the other hand, the GPU is more promising for large number of FFT's of large sizes. The results also confirm that the FPGA based implementation is faster then the built-in IP-core modules of Xilinx. A hardware synthesis for FPGA is also provided.

关键词： Fast Fourier Transform Field Programmable Gate Arrays Graphic Processing Units open computing language Verilog HDL

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SOFTWARE DEFINED RADIO IMPLEMENTATION OF ADAPTIVE NONLINEAR DIGITAL SELF-INTERFERENCE CANCELLATION FOR MOBILE INBAND FULL-DUPLEX RADIO

SOFTWARE DEFINED RADIO IMPLEMENTATION OF ADAPTIVE NONLINEAR ...

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IEEE Global Conference on Signal and Information Processing (GlobalSIP)

作者： AghababaeeTafreshi, Mona Koskela, Matias Korpi, Dani Jaaskelainen, Pekka Valkama, Mikko Takala, Jarmo Tampere Univ Technol POB 553 FI-33720 Tampere Finland

ISBN: (纸本)9781509045457

Inband full-duplex radio transceivers offer enhanced spectral efficiency by transmitting and receiving simultaneously at the same frequency. However, deployment of such systems is challenging due to the inherent self-interference stemming from coupling of the transmit signal to the receiver. Furthermore, to track changes in the time-varying self-interference channel, the process needs to be self-adaptive. Thus, advanced solutions are required to efficiently mitigate the self-interference. With the current rise in parallel architectures due to limitations of performance enhancement by higher clock frequencies, multi-core platforms are considered as viable solutions for implementing such advanced techniques. This paper describes a progranunable implementation of an adaptive nonlinear digital self-interference cancellation method for full-duplex transceivers on two mobile GPUs and a multi-core CPU. The results demonstrate the feasibility of realizing a real-time software-based implementation of digital self-interference cancellation on a mobile GPU, in case of a 20 MHz cancellation bandwidth.

关键词： 5G Full-duplex self-interference cancellation graphics processing units open computing language

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Decision Support System for Real-Time Trading based on On-Line Learning and Parallel computing Techniques 7

Decision Support System for Real-Time Trading based on On-Li...

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7th International Conference on Cloud computing and Big Data (CCBD)

作者： Chen, Chiao-Ting Huang, Shih-Jung Chang, Yang Hsiao, Chih-Yen Lin, Jiun-Yi Huang, Szu-Hao Natl Chiao Tung Univ Dept Informat Management & Finance Hsinchu Taiwan Natl Chiao Tung Univ Inst Informat Management Hsinchu Taiwan

ISBN: (纸本)9781509035557

A novel intraday algorithmic trading strategy is developed based on various machine learning techniques and paralleled computing architectures in this paper. The proposed binary classification framework can predict the price trends of Taiwan stock index futures after thirty minutes. Traditional learning-based approaches collect all samples during the training period as the learning materials. The major contribution of this paper is to collect a subset of similar historical financial data to train the real-time trading model. This goal can be achieved by an on-line learning technique which is required to calculate an accurate model with training time limitation. In addition, the proposed joint-AdaBoost algorithm is to improve the system performance based on the concept of paired feature learning and planar weak classifier design. The core execution components in this algorithm can be further accelerated with the aid of open computing language (openCL) parallel computing platform. The experimental results show that the proposed learning algorithm can improve the prediction accuracy of final classifier from 53.8% to 61.68%. Compared to the pure CPU implementation, the openCL version which uses CPU and GPGPU simultaneously can reduce the calculation time around 83.02 times. The efficiency improvement can decrease the delay of investment opportunity which is a critical issue in real-time financial decision support system application. To sum up, this paper proposed a novel learning framework based on joint-AdaBoost algorithm with similar learning samples and openCL parallel computation. The extended financial decision support system is also proven to work effectively and efficiently in our simulation experiments to trade the Taiwan stock index futures.

关键词： joint-AdaBoost Algorithmic trading Decision support system Parallel computing open computing language

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Empowering Reconfigurable Platforms for Massively Parallel Applications

Empowering Reconfigurable Platforms for Massively Parallel A...

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作者： Purkayastha, Arnab A. The University of North Carolina at Charlotte

学位级别：Ph.D., Doctor of Philosophy

The availability of openCL for FPGAs along with High-Level Synthesis tools have made them an attractive platform for implementing compute-intensive massively parallel applications. FPGAs with their customizable data-path, deep pipelining abilities and enhanced power efficiency features offer the most viable solutions for programming and integrating them with heterogeneous platforms. However, openCL for FPGAs raise many design challenges which require an in-depth understanding to better utilize their enormous capabilities. Inefficient routing of data, high number of memory stalls exposed to execution and under-utilization of FPGA resources are significant execution bottlenecks that overshadow the advantages of data-path customization. Furthermore, leveraging openCL parallelism abilities and throughput oriented principles is paramount to the success of FPGAs in the high performance computing environment. In this research, we identify, analyze and categorize the architectural differences between the openCL parallel programming model and FPGA execution semantic. We propose a generic taxonomy for classifying FPGA parallelism potential to the fullest. To benefit massive thread-level parallelism, we introduce a unique LLVM based automation tool to decouple memory access from computation, thereby hiding memory stalls from the execution path. We further present a novel parallelism granularity that separates kernels to split them into data-path and memory-path (memory read/write) that work concurrently to overlap the computation of current threads with the memory access of future threads. We validate these principles on the Xilinx based AWS Cloud FPGA platform. We then conduct a thorough investigation into the scalability of openCL coarse-grain parallelism, as well as an examination of Compute Unit(CU) replication, Double Data Rate (DDR) and Burst Transfer (BT) optimizations on Cloud FPGAs. To address the issue of programming challenges, we present generic template(s) and a f

关键词： Cloud FPGA Field programmable gate array High level synthesis Low level virtual machine openCL Parallelism open computing language Architecture

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Mac OS X Snow Leopard Bible 1

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丛书名： Bible

2009年

作者： Gruman Galen Hattersley Mark

ISBN: (数字)9780470559413

ISBN: (纸本)9780470453636

Tame the very latest Mac OS X cat, Snow Leopard 10.6Snow Leopard moves faster and roars louder than its predecessor, and this comprehensive guide shows you all the ways to get the most out of this powerful new cat. Explore everything from its muscular handling of applications and streaming media to its new, game-changing support of Microsoft's ActiveSync® technology. Get set up on Snow Leopard 10.6, learn professional-level security tools, and discover secret tricks and workarounds with this essential guide. Install, set up, secure, and explore Mac OX 10.6 Snow Leopard Connect to a network, work with MobileMe, and share files Meet Grand Central Dispatch and jet-propel your apps with parallel processing Get up to speed on open CL, for faster general performance Run Windows® applications and exchange files with Windows PCs Go beyond the basics with AppleScript®, the Automator, and Unix® commands

关键词： Mac OS X Snow Leopard Mac OS X Snow Leopard Apple?s new operating system Apple?s new OS Snow Leopard OS 64 bit memory Grand Central on Snow Leopard QuickTime X open CL open computing language Microsoft Exchange 2007 new features of Snow Leopard new software of Snow Leopard changes to Snow Leopard

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