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Bio-inspired discontinuous composite materials with a machine learning optimized architecture

COMPOSITE STRUCTURES 2025年 351卷

作者： Loutas, Theodoros Oikonomou, Athanasios Rekatsinas, Christoforos Univ Patras Dept Mech Engn & Aeronaut Rion 26504 Greece Inst Informat & Telecommun Natl Ctr Sci Res Demokritos Software & Knowledge Engn Lab Athens 15341 Greece

Bio-inspired hierarchical discontinuous fibrous composite materials are investigated with the aim of achieving enhanced pseudo-ductility and elevated toughness. A novel methodology is proposed to search quickly and efficiently through the vast design space of the geometrical parameters of the discontinuities, combining advanced numerical simulations of the material's mechanical behavior with state-of-the-art Machine Learning approaches, such as Active Learning. A continuum mesoscale-based numerical model is developed to simulate the mechanical behavior of discontinuous composites under three-point bending loading and is utilized in a sequential Bayesian optimization scheme that iteratively searches for the material architecture that maximizes toughness. Five independent geometrical variables related to the size and exact topology of the discontinuities form a vast five-dimensional design space of more than 2.6 million possible combinations. In this space, the proposed methodology efficiently identifies, after 100 iterations, a remarkable optimal configuration that increases the material's toughness by more than 100%, with a knock-down effect on the ultimate bending strength of only 10%.

关键词： Bio-inspired composites optimized architecture Toughness Active learning Material informatics

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Slim MobileNet: An Enhanced Deep Convolutional Neural Network 18

Slim MobileNet: An Enhanced Deep Convolutional Neural Networ...

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18th International Multi-Conference on Systems, Signals & Devices (SSD)

作者： Bouguezzi, Safa Faiedh, Hassene Souani, Chokri Univ Monastir Microelect & Instrumentat Lab Monastir Tunisia Univ Monastir Fac Sci Monastir Monastir Tunisia Univ Sousse Higher Inst Appl Sci & Technol Sousse Sousse Tunisia

ISBN: (纸本)9781665414937

The Convolutional Neural Network (CNN) is dominant in computer vision applications such as object detection, traffic sign recognition, image classification, face recognition applications, etc. The MobileNet model is a CNN architecture that was constructed to be implemented on an embedded board. However, there are constraints of such architecture for the hardware deployment, which is the limited memory of micro-controller units. This paper proposes an enhanced version of MobileNet that verify the condition to be implemented on an embedded board while improved the accuracy. The proposed model obtained the name of Slim Mobile Net because of its small size of 7.3 MB. Slim MobileNet has fewer number of layers, improved accuracy while depreciating the overall size of the model and lower average time compared to the MobileNet-Vl model. We achieve a significant accuracy by replacing the ReLU activation function with the Tanh Exponential (TanhExp) activation function and by making some modifications in the unit of depthwise separable convolution. The small size of Slim MobileNet is occurred by dropping some layers from the original architecture of baseline MobileNet. The experiment is realized using the CIFAR-10 database.

关键词： Convolutional Neural Network (CNN) MobileNet Tanh Exponential (TanhExp) Activation Depthwise Separable Convolutions optimized architecture Pytorch CIFAR-10

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Quantum repeater architecture with hierarchically optimized memory buffer times

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QUANTUM SCIENCE AND TECHNOLOGY 2019年第2期4卷

作者： Santra, Siddhartha Jiang, Liang Malinovsky, Vladimir S. Idsantralgmailcom US Army Res Lab Adelphi MD 20783 USA Yale Univ Dept Appl Phys & Phys New Haven CT 06520 USA Yale Univ Yale Quantum Inst New Haven CT 06511 USA

We propose a quantum repeater protocol and architecture that mitigates decoherence of the entangled states by optimizing the quantum memory buffer time. The protocol maximizes the rate of distillable entanglement in the average accessed state at all nesting levels. The achievable rate is higher by orders of magnitude in comparison to a canonical protocol that does not optimize the buffer time. The advantage of the proposed design is observed for all nesting levels of the repeater for technologically feasible memory quality, entanglement generation and swapping success probabilities.

关键词： quantum repeaters memory decoherence optimized architecture

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Spatial Multiplexing in a Cavity-Enhanced Quantum Memory 12

Spatial Multiplexing in a Cavity-Enhanced Quantum Memory

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Conference on Advances in Photonics of Quantum Computing, Memory, and Communication XII

作者： Kunz, Paul D. Santra, Siddhartha Meyer, David H. Castillo, Zachary A. Malinovsky, Vladimir S. Cox, Kevin C. US Army Res Lab Adelphi MD 20783 USA Univ Maryland Dept Phys College Pk MD 20742 USA

ISBN: (数字)9781510625099

ISBN: (纸本)9781510625099

We present a multiplexed quantum repeater protocol based on an ensemble of laser-cooled and trapped rubidium atoms inside an optical ring cavity. We have already demonstrated strong collective coupling in such a system and have constructed a multiplexing apparatus based on a two-dimensional acousto-optical deflector. Here, we show how this system could enable a multiplexed quantum repeater using collective excitations with non-trivial spatial phase profiles (spinwaves). Calculated entanglement generation rates over long distances reveal that such a multiplexed ensemble-cavity platform is a promising route towards long distance quantum entanglement and networking.

关键词： Quantum Repeater Quantum Memory Optical Cavity Multiplexing optimized architecture

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Onboard optimized Hardware Implementation of JPEG-LS Encoder Based on FPGA

Onboard Optimized Hardware Implementation of JPEG-LS Encoder...

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Conference on Satellite Data Compression, Communications, and Processing VIII

作者： Wei, Wen Lei, Jie Li, Yunsong Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China

ISBN: (纸本)9780819492319

A novel hardware implementation of JPEG-LS Encoder based on FPGA is introduced in this paper. Using a look-ahead technique, the critical delay paths of LOCO-I algorithm, such as feedback-loop circuit of parameters updating, are improved. Then an optimized architecture of JPEG-LS Encoder is proposed. Especially, run-mode encode process of JPEG-LS is covered in the architecture as well. Experiment results show that the circuit complexity and memory consumption of the proposed structure are much lower, while the data processing speed is much higher than some other available structures. So it is very suited for applying high-speed lossless compression of satellite sensing image onboard.

关键词： JPEG-LS Encoder look-ahead technique optimized architecture run-mode encoder

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High Speed and Bi-mode Image Compression Core for Onboard Space Application

High Speed and Bi-mode Image Compression Core for Onboard Sp...

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International Conference on Space Information Technology 2009

作者： Wang, Huaichao Chen, Jun Gu, Xiaodong Chen, Xiaomin Chinese Acad Sci Ctr Space Sci & Appl Res Beijing 100190 Peoples R China

ISBN: (纸本)9780819480798

This paper presents a bi-mode, high performance Discrete Wavelet Transform-based image compression core for future spacecrafts and micro-satellites. The hardware solution proposed here exploits an optimized CCSDS IDC algorithm and consists of a lossless mode and a lossly mode. The throughput of the core is improved 40 times using parallel architecture and pipeline technique, and a data rate of about 12.5M pixles/s can be sustained at 50MHz for the lossly mode. The experimental results indicate that this core has high performance at coding efficiency, data rate and error containment for both of the two modes.

关键词： CCSDS image compression bi-mode DWT optimized architecture bit plane coder

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Optimization of Processor architecture for Image Edge Detection Filter

Optimization of Processor Architecture for Image Edge Detect...

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12th International Conference on Computer Modelling and Simulation (UKSim)

作者： Osman, Zahraa Elhassan M. Hussin, Fawnizu Azmadi Ali, Noohul Basheer Zain Univ Teknol PETRONAS Tronoh 31750 Perak Malaysia

ISBN: (纸本)9780769540160

In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing the frequency of memory access. Direct hardware implementation as proposed by previous works require most image pixels to be read from memory up to six times and transferred into the Sobel edge detection processor. In our work, we try to reduce the number of pixels read therefore affecting tremendous potential speed suitable for the embedded video processing applications.

关键词： component-Sobel edge detection filter FPGA optimized architecture

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FPGA based high-speed system solutions for innovative maskless lithography systems

FPGA based high-speed system solutions for innovative maskle...

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Conference on Photomask and Next-Generation Lithography Mask Technology XIII

作者： Voss, Sven-Hendrik Talmi, Maati Heinrich Hertz Inst Nachrichtentech Berlin GmbH Fraunhofer Inst Telecommun Einsteinufer 37 D-10587 Berlin Germany

ISBN: (纸本)0819463582

Maskless lithography is one of the possible solutions to manage the escalating mask costs and demands for faster production cycles. One of the major issues with the mdskless lithography technology however is the management and transfer of the enormous data volumes required to define the chip structures. Ensuring competitive and reliable operation requires dedicated preparation and buffering of the lithography data to be transmitted to the exposure unit. An optimized dedicated architecture and careful signal integrity design for proper functionality are needed due to the high data rates and the highly parallelized system operation. This paper presents the implementation aspects and the design of a high-speed transmission system solution for maskless lithography systems. The introduced solution treats a field programmable gate array (FPGA) based implementation for a latency-sensitive high speed lithography system.

关键词： maskless lithography high-speed buffer FPGA implementation PCB optimized architecture

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