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Measurement and Simulation (ATOMS), Advanced Topics on

作者： Iulian Busu Alexandra-Mihaela Enescu Horia-Răzvan Enescu Călin Bîră Dept. of Electronic Technologies and Reliability National University of Science and Technology Politehnica Bucharest Romania Dept. of Devices Circuits and Architectures National University of Science and Technology Politehnica Bucharest Romania

ISBN: (数字)9798350358377

ISBN: (纸本)9798350358384

This work presents an exploratory study of how ChatGPT, the AI assistant developed by OpenAI, can support engineers in developing C and ASM code for low-cost, memory-constrained microcontrollers (PIC10F200). We evaluated ChatGPT’s ability to assist with writing the source code and found that it demonstrated to deliver faster results with competitive performance levels for C language, in almost ready-to-run programs, provided that the specific timings and resource allocation is performed by an optimizing compiler. In ASM however, ChatGPT was barely adequate, its performance being lower than average young engineers, despite intensive help received from an experienced human programmer.

关键词： Embedded systems optimizing compilers Microcontrollers Source coding Writing Chatbots Timing Resource management Artificial intelligence Optimization

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Efficient Automatic Scheduling of Imaging and Vision Pipelines for the GPU

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PROCEEDINGS OF THE ACM ON PROGRAMMING LANGUAGES-PACMPL 2021年第OOPSLA期5卷 1–28页

作者： Anderson, Luke Adams, Andrew Ma, Karima Li, Tzu-Mao Jin, Tian Ragan-Kelley, Jonathan MIT 77 Massachusetts Ave Cambridge MA 02139 USA Adobe Mountain View CA USA Univ Calif San Diego San Diego CA 92103 USA

We present a new algorithm to quickly generate high-performance GPU implementations of complex imaging and vision pipelines, directly from high-level Halide algorithm code. It is fully automatic, requiring no schedule templates or hand-optimized kernels. We address the scalability challenge of extending search-based automatic scheduling to map large real-world programs to the deep hierarchies of memory and parallelism on GPU architectures in reasonable compile time. We achieve this using (1) a two-phase search algorithm that first 'freezes' decisions for the lowest cost sections of a program, allowing relatively more time to be spent on the important stages, (2) a hierarchical sampling strategy that groups schedules based on their structural similarity, then samples representatives to be evaluated, allowing us to explore a large space with few samples, and (3) memoization of repeated partial schedules, amortizing their cost over all their occurrences. We guide the process with an efficient cost model combining machine learning, program analysis, and GPU architecture knowledge. We evaluate our method's performance on a diverse suite of real-world imaging and vision pipelines. Our scalability optimizations lead to average compile time speedups of 49x (up to 530x). We find schedules that are on average 1.7x faster than existing automatic solutions (up to 5x), and competitive with what the best human experts were able to achieve in an active effort to beat our automatic results.

关键词： optimizing compilers Halide

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NOVLI-ISA: A Novel Optimized Variable-Length Inclusive Instruction Set Architecture for RV32I/E Architecture

NOVLI-ISA: A Novel Optimized Variable-Length Inclusive Instr...

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East-West Design & Test Symposium (EWDTS)

作者： Amer Dyab H. Fatih Ugurdag Electrical and Electronics Engineering Dept Ozyegin University Istanbul Türkiye

ISBN: (数字)9798331515768

ISBN: (纸本)9798331515775

This paper proposes a Novel, Optimized Variable-Length Inclusive ISA for RV32I/E architectures, namely, NOVLI-ISA. The main objective of this work is to reduce the code size and, if possible, the power consumption. The proposed ISA introduces new general and tailored functions within its flexible structure. The proposed ISA is demonstrated using a sample RV32I CPU with the necessary hardware modifications. Furthermore, to evaluate its feasibility, a dedicated batch optimizer was implemented for machine code compression and quantitative analysis of typical storage reduction for different programs.

关键词： Codes Power demand Statistical analysis optimizing compilers Instruction sets Memory management Hardware Flexible structures Standards Optimization

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Improving Qubit Routing by Using Entanglement Mediated Remote Gates

Improving Qubit Routing by Using Entanglement Mediated Remot...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Gurleen Padda Edwin Tham Aharon Brodutch Dave Touchette Department of Computer Science Institut Quantique Université de Sherbrooke Sherbrooke Canada IonQ Canada Toronto Canada

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

Near-term quantum computers often have connectivity constraints, i.e. restrictions, on which pairs of qubits in the device can interact. Optimally mapping a quantum circuit to a hardware topology under these constraints is a difficult task. While numerous approaches have been proposed to optimize qubit routing, the resulting gate count and depth overheads of the compiled circuits remain high due to the short-range coupling of qubits in many near-term devices. Resource states, such as Bell or Einstein-Podolsky-Rosen (EPR) pairs, can be used to mediate operations that facilitate long-range interactions between qubits. In this work, we studied some of the practical trade-offs involved in using resource states for qubit routing. We developed a method that leverages an existing state-of-the-art compiler to optimize the routing of circuits with both standard gates and EPR mediated remote controlled-NOT gates. This was then used to compile different benchmark circuits for a square grid topology, where a fraction of the qubits are used to store EPR pairs. We demonstrate that EPR-mediated operations can substantially reduce the total number of gates and depths of compiled circuits when used with an appropriate optimizing compiler that accounts for practical overheads. Our results highlight the relevance of developing efficient compilation tools that can integrate EPR-mediated operations.

关键词： optimizing compilers Qubit Circuits Logic gates Benchmark testing Routing Hardware Topology Quantum circuit Standards

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LCOC: A Low-cost optimizing Compiler for Large Scale Quantum Programs Towards Realistic Hardware

LCOC: A Low-cost Optimizing Compiler for Large Scale Quantum...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yu Zhu Jinchen Xu Qing Mu Hongru Yang Xiaodong Ding Qiming Du Zheng Shan Laboratory for Advanced Computing and Intelligence Engineering China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Quantum compilers play an essential role in the translation of quantum algorithms on quantum hardware. As the size of quantum programs increases, the problem of extreme compilation overhead becomes apparent. To address this problem, compilation frameworks with high-level intermediate representations such as QCOR have been introduced. However, these frameworks still face significant overhead from qubit mapping and optimizing sequence redundancy, resulting in challenges when compiling circuits to realistic hardware. In our paper, a low-cost optimizing compiler (LCOC) is proposed, which addresses the overhead in qubit mapping and enhanced the optimization capabilities. A qubit mapping optimizer based on the LLVM Polly is introduced in LCOC, which implements an efficient mapping of quantum programs containing specific loop types. While achieving low-cost mapping, it considerably reduces the depth of the circuit. We also implement an optimization sequence generator that leverages the modularity of LLVM and iterative compilation to provide LCOC with a more flexible and efficient optimization sequence. We conduct experiments with 100+ qubit circuits. Experiments show that LCOC is up to 1540× faster compared to Qiskit and 74× faster compared to QCOR in compile time. The average speedup relative to Qiskit and QCOR are 194× and 8.64×, respectively. In addition, it can effectively reduce the circuit depth by 50.32% compared to Qiskit and 83.5% compared to QCOR on average.

关键词： Translation Quantum algorithm optimizing compilers Qubit Circuits Redundancy Hardware Generators Iterative methods Optimization

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A Survey of Optimized Compiler Using Advanced Machine learning and Deep Learning Techniques

A Survey of Optimized Compiler Using Advanced Machine learni...

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Cybernetics, Cognition and Machine Learning Applications (ICCCMLA), IEEE International Conference on

作者： Lal Bahadur Pandey Manisha Sharma Rajesh Tiwari Radhe Shyam Panda Partha Roy Dept. of CSE(AI & ML) CMR Engineering College Hydrabad India Dept. of ETC Bhilai Institute of Technology Durg Chhattisgarh India Dept. of CSE CMR Engineering College Hydrabad India Dept. of CSE Bhilai Institute of Technology Durg Chhattisgarh India

ISBN: (数字)9798331505790

ISBN: (纸本)9798331505806

optimizing compilers is a difficult and time-consuming task, especially when done by hand. As far as we know, the compiler handles both translation and optimization. An efficient compiler system can become more automated and simple, as evidenced by recent studies using deep learning and machine learning approaches. Model training, prediction, optimization, and feature selection are handled by most machine learning and deep learning methods. In this case, choosing the optimal characteristics is necessary in order to use deep learning and machine learning techniques to enhance the optimization quality. This study examines various approaches that might be utilized to enhance and refine the quality of the chosen heuristics as well as the general quality of machine learning and deep learning models in order to boost the compiler's efficiency. The phase-ordering problem, the amount of iterative program evaluations, and the time needed to obtain the best forecast are only a few of the many subjects covered by these approaches.

关键词： Deep learning Surveys Training Translation optimizing compilers Artificial neural networks Predictive models Iterative methods Optimization Unsupervised learning

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Automatic Generation of OpenCL Code through Polyhedral Compilation with LLM

Automatic Generation of OpenCL Code through Polyhedral Compi...

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Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Marek Palkowski Mateusz Gruzewski West Pomeranian University of Technology in Szczecin Szczecin Poland

ISBN: (数字)9788396960160

ISBN: (纸本)9798350359718

In recent years, a multitude of AI solutions has emerged to facilitate code generation, commonly known as Language Model-based Programming (LLM). These tools empower programmers to automate their work. Automatic programming also falls within the domain of optimizing compilers, primarily based on the polyhedral model, which processes loop nests concentrating most computations. This article focuses on harnessing LLM tools to generate OpenCL code for non-serial polyadic dynamic programming kernels. [1] We have chosen the Nussinov RNA folding computational task, previously employed to test polyhedral compilers in optimizing kernels with non-uniform dependences. The code generated in OpenMP by polyhedral optimizers is limited to CPU computations. We automatically convert it into the OpenCL standard using ChatGPT-3.5 through its source-to-source queries to extend the number of possible platforms. The validity and efficiency of the generated code were verified on various CPUs and GPUs from different manufacturers.

关键词： Codes optimizing compilers Computational modeling RNA Xenon Writing Kernel Standards Optimization Software development management

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Basic Operations And Structure Of An FPGA Accelerator For Parallel Bit Pattern Computation

Basic Operations And Structure Of An FPGA Accelerator For Pa...

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IEEE International Conference on Rebooting Computing (ICRC)

作者： Dietz, Henry Eberhart, Paul Rule, Ashley Univ Kentucky Elect & Comp Engn Lexington KY 40506 USA

ISBN: (纸本)9781665423328

Parallel Bit Pattern computing (PBP) has been proposed as a way to dramatically reduce power consumption per computation by minimizing the total number of gate operations. In part, this reduction is accomplished by employing aggressive compiler optimization technology to gate-level representations of computations at runtime. Massive SIMD parallelism is used to obtain speedups while executing the optimized bit-serial code. However, the PBP model also can potentially exponentially reduce the number of active gates for each such operation by recognizing and operating on symbolically-compressed patterns of bits, rather than on each individual bit within a vector. This not only provides for efficient execution of traditional parallel code, but by using bit vectors to represent entangled superposition, enables quantum-like computation to be efficiently implemented using conventional circuitry. Building on lessons learned from various software and Verilog prototypes, this paper proposes a new set of basic operations and interface structure suitable for using inexpensive Xilinx Zynq-7000 boards to implement FGPA-hardware-accelerated PBP computation. Emphasis is on how these operations will implement quantum-like computation, as the first prototype system is currently still under development.

关键词： Computer Architecture Parallel Bit Pattern Computing SIMD optimizing compilers Logic Optimization

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Improved Basic Block Reordering

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IEEE TRANSACTIONS ON COMPUTERS 2020年第12期69卷 1784-1794页

作者： Newell, Andy Pupyrev, Sergey Facebook Inc Menlo Pk CA 94025 USA

Basic block reordering is an important step for profile-guided binary optimization. The state-of-the-art goal for basic block reordering is to maximize the number of fall-through branches. However, we demonstrate that such orderings may impose suboptimal performance on instruction and I-TLB caches. We propose a new algorithm that relies on a model combining the effects of fall-through and caching behavior. As details of modern processor caching is quite complex and often unknown, we show how to use machine learning in selecting parameters that best trade off different caching effects to maximize binary performance. An extensive evaluation on a variety of applications, including Facebook production workloads, the open-source compilers Clang and GCC, and SPEC CPU benchmarks, indicate that the new method outperforms existing block reordering techniques, improving the resulting performance of applications with large code size. We have open sourced the code of the new algorithm as a part of a post-link binary optimization tool, BOLT.

关键词： Optimization Fasteners Measurement Machine learning Facebook Central Processing Unit Tools Code generation code layout optimizing compilers profile-guided optimizations graph algorithms

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A Succinct Summary of the Solar MPPT Utilizing a Diverse optimizing Compiler

A Succinct Summary of the Solar MPPT Utilizing a Diverse Opt...

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International Conference on Contemporary Computing and Informatics (IC3I)

作者： N. Pushpalatha S. Jabeera N. Hemalatha Vandana Sharma Balamurugan Balusamy R. Yuvaraj Department of Electrical and Electronics Engineering Sri Eshwar College of Engineering Coimbatore Tamilnadu India Department of Electrical and Electronics Engineering Pollachi Institute of Technology Pollachi Tamilnadu India Amity Institute of Information Technology India Shiv Nadar Institute of Eminence Delhi-NCR India Department of Electrical and Electronics Engineering Excel Engineering College Namakkal Tamilnadu India

AI approaches have been widely used for MPPT in solar power systems in the recent decade. Conventional MPPT can’t track GMPP under partial shade (PSC). A solar panel’s power-voltage output curve has one GMPP and several LMPPS (MPPs). AI must be integrated into MPPT to track GMPP and improve its efficiency and performance. Each AI-based MPPT approach has its own pros and cons. In general, AI-based MPPT approaches have quick convergence speeds, low steady-state oscillations, and high effectiveness. AI-based MPPT is computationally intensive and expensive. This research compares the categorization and performance of various AI-based MPPT approaches. In the proposed work it is found that ANN algorithm is less complex, more efficient in tracking ability, periodic tuning is available. FLC deserves the merit of efficient implementation with periodic tuning. PSO, ACO, DE, GA has a rapid convergence speed. GWO/FOAhas more system independency and Even though the tracking is not possible RMO/CSis one of the most efficient algorithms.

关键词： optimizing compilers Complexity theory Steady-state Power systems Artificial intelligence Informatics Tuning

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