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MEMORY MANAGEMENT FOR DATA-FLOW PROGRAMMING OF MULTIRATE SIGNAL-PROCESSING ALGORITHMS

IEEE TRANSACTIONS ON SIGNAL PROCESSING 1994年第5期42卷 1190-1201页

作者： BHATTACHARYYA, SS LEE, EA Department of Electrical Enginneering and Computer Science University of California

Managing the buffering of data along arcs is a critical part of compiling a synchronous dataflow (SDF) program. This paper shows how dataflow properties can be analyzed at compile-time to make buffering more efficient. Since the target code corresponding to each node of an SDF graph is normally obtained from a hand-optimized library of predefined blocks, the efficiency of data transfer between blocks is often the limiting factor in how closely an SDF compiler can approximate meticulous manual coding. Furthermore, in the presence of large sample-rate changes, straightforward buffering techniques can quickly exhaust limited on-chip data memory, necessitating the use of slower external memory. The techniques presented in this paper address both of these problems in a unified manner.

关键词： Dataflow Programming Code Generation Memory Allocation Graphical Programming optimizing compilers Multirate Signal Processing.

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Compiler design issues for embedded processors

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IEEE DESIGN & TEST OF COMPUTERS 2002年第4期19卷 51-58页

作者： Leupers, R Rhein Westfal TH Aachen Inst Integrated Signal Proc Syst D-52056 Aachen Germany

The growing complexity and high efficiency requirements of embedded systems call for new code optimization techniques and architecture exploration, using retargetable C and C++ compilers.

关键词： optimizing compilers Computer architecture Embedded system Program processors Design optimization Iterative methods Application specific processors Software tools Hardware Process design

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Compiler-directed energy optimization for parallel-disk-based systems

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2007年第9期18卷 1241-1257页

作者： Son, Seung Woo Chen, Guangyu Ozturk, Ozcan Kandemir, Mahmut Choudhary, Alok Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Microsoft Corp Redmond WA 98052 USA Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural-level techniques to reduce disk power by taking advantage of idle periods experienced by disks. Although such techniques have been known to be effective in certain cases, they share a common drawback: They operate in a reactive manner, i.e., they control disk power by observing past disk activity (for example, idle and active periods) and estimating future ones. Consequently, they can miss opportunities for saving power and incur significant performance penalties due to inaccuracies in predicting idle and active times. Motivated by this observation, this paper proposes and evaluates a compiler-driven approach to reducing disk power consumption of array-based scientific applications executing on parallel architectures. The proposed approach exposes disk layout information to the compiler, allowing it to derive the disk access pattern, i.e., the order in which parallel disks are accessed. This paper demonstrates two uses of this information. First, we can implement proactive disk power management, i.e., we can select the most appropriate power-saving strategy and disk-preactivation strategy based on the compiler-predicted future idle and active periods of parallel disks. Second, we can restructure the application code to increase the length of idle disk periods, which leads to better exploitation of available power-saving capabilities. We implemented both these approaches within an optimizing compiler and tested their effectiveness using a set of benchmark codes from the Spec 2000 suite and a disk power simulator. Our results show that the compiler-driven disk power management is very promising. The experimental results also reveal that, although proactive disk power management is very effective, code restructuring for disk power achieves additional energy savings across all the benchmarks tested, and these savings a

关键词： disk subsystem I/O traces optimizing compilers power-aware computing parallel I/O

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INTELS 80960 - AN ARCHITECTURE OPTIMIZED FOR EMBEDDED CONTROL

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IEEE MICRO 1988年第3期8卷 63-76页

作者： RYAN, DP Intel Corporation

Important features and capabilities of the 80960 are briefly examined, and an overview of its architecture is given. A detached discussion is presented of the register model, core instruction set, register operations, memory operations, control operations instruction cache, user-supervisor protection, interrupts, faults, and debug support.

关键词： Clocks Microarchitecture Out of order Registers Silicon Memory management optimizing compilers Design optimization Pipelines Reduced instruction set computing

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DEFINING, ANALYZING, AND TRANSFORMING PROGRAM CONSTRUCTS

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IEEE PARALLEL & DISTRIBUTED TECHNOLOGY 1994年第1期2卷 32-39页

作者： LI, JK WOLFE, M OREGON GRAD INST PORTLAND OR 97291 USA

We have developed a framework for analyzing the behavior and relations of various sequential and parallel control constructs, which we can nest in a very general way. A simple yet powerful scheme defines the order of data accesses in a program, and provides a well-founded semantic structure for nested constructs. When defining parallel languages or extensions to current languages, designers can use this framework to define how each new feature interacts with the language's other features. Because our approach is based on well-known dependence analysis techniques, it is practical for compiler implementation. It determines which behavior the compiler and system must preserve while allowing aggressive automatic optimization. Instead of being confined to a single programming paradigm, programmers can use the most appropriate constructs for the application, and the compiler can transform and optimize the program for different parallel or sequential architectures.

关键词： Parallel languages optimizing compilers Programming profession Program processors Parallel processing Testing Computer architecture Workstations Supercomputers Computer languages

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PERFORMANCE COMPARISON OF LARGE-SCALE SCIENTIFIC COMPUTERS - SCALAR MAINFRAMES, MAINFRAMES WITH INTEGRATED VECTOR FACILITIES, AND SUPERCOMPUTERS

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COMPUTER 1987年第3期20卷 10-23页

作者： JORDAN, KE Exxon Research and Engineering Company

First Page of the Article

关键词： Large scale integration Supercomputers Large-scale systems Scientific computing optimizing compilers Costs Equations Arithmetic Vector processors Computer architecture

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Changing interaction of compiler and architecture

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COMPUTER 1997年第12期30卷 51-&页

作者： Adve, SV Burger, D Eigenmann, R Rawsthorne, A Smith, MD Gebotys, CH Kandemir, MT Lilja, DJ Choudhary, AN Fang, JZ Yew, PC UNIV MINNESOTA DEPT ECEMINNEAPOLISMN 55455 UNIV WISCONSIN MADISONWI PURDUE UNIV SCH ELECT & COMP ENGNW LAFAYETTEIN 47907 UNIV MANCHESTER MANCHESTER M13 9PLLANCSENGLAND HARVARD UNIV DIV ENGN & APPL SCICAMBRIDGEMA 02138 UNIV WATERLOO WATERLOOON N2L 3G1CANADA SYRACUSE UNIV SYRACUSENY 13244 NORTHWESTERN UNIV EVANSTONIL 60208 INTEL CORP MICROCOMP RES LABSRES GRPSANTA CLARACA UNIV ILLINOIS CTR SUPERCOMP RES & DEVURBANAIL 61801

With recent developments in compilation technology and architectural design, the line between traditional hardware and software roles has become increasingly blurred. The compiler can now see the processor's inner structure, which lets architects exploit sophisticated program analysis techniques to hide branch and memory access delays, for example. Processors can now implement register renaming and dynamic instruction-scheduling algorithms directly in the hardware-something that was once exclusively the compiler's job. A similar shift is occurring in optimizing compilers for parallel machines. To parallelize a larger class of applications, compiler writers are moving beyond static transformations and exploring techniques that rely on runtime decisions or hardware support. This increased blurring of compile-time and runtime optimizations opens many new research opportunities, particularly for program optimization-a task typically performed entirely at compile time. This article describes an optimization continuum and shows how different classes-of optimizations fall within it.

关键词： Hardware optimizing compilers Program processors Information analysis Computer architecture Runtime environment Delay Registers Scheduling algorithm Parallel machines

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Affine Modeling of Program Traces

引用

IEEE TRANSACTIONS ON COMPUTERS 2019年第2期68卷 294-300页

作者： Rodriguez, Gabriel Kandemir, Mahmut T. Tourino, Juan Univ A Coruna Dept Comp Engn La Coruna 15071 Spain Penn State Univ Dept Comp Sci & Engn State Coll PA 16801 USA

A formal, high-level representation of programs is typically needed for static and dynamic analyses performed by compilers. However, the source code of target applications is not always available in an analyzable form, e.g., to protect intellectual property. To reason on such applications it becomes necessary to build models from observations of its execution. This paper presents an algebraic approach which, taking as input the trace of memory addresses accessed by a single memory reference, synthesizes an affine loop with a single perfectly nested statement that generates the original trace. This approach is extended to support the synthesis of unions of affine loops, useful for minimally modeling traces generated by automatic transformations of polyhedral programs, such as tiling. The resulting system is capable of processing hundreds of gigabytes of trace data in minutes, minimally reconstructing 100 percent of the static control parts in PolyBench/C applications and 99.9 percent in the Pluto-tiled versions of these benchmarks.

关键词： Program modeling optimizing compilers polyhedral optimization memory traces

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Evaluation of min/max instructions for fuzzy information processing

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IEEE TRANSACTIONS ON FUZZY SYSTEMS 1996年第3期4卷 369-374页

作者： Watanabe, H Chen, D Konuri, S UNIV N CAROLINA DEPT COMP SCICHAPEL HILLNC 27514

We report the results of dynamic measurements which evaluate the effectiveness of an application specific microprocessor for fuzzy control and fuzzy information processing, We propose to specialize an architecture of microprocessor for fuzzy theoretic operations using quantitative techniques developed by designers of reduced instruction set computer (RISC), In particular, an introduction of specialized instructions is considered, Experimental results show that we can achieve as high as 2.5 speed up of a program for fuzzy control by introducing two instructions-min and max.

关键词： Information processing Delay Microprocessors Fuzzy sets Fuzzy control Reduced instruction set computing Application specific integrated circuits optimizing compilers Application software Fuzzy logic

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SKOL - A SYSTEM FOR LOGIC SYNTHESIS AND TECHNOLOGY MAPPING

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第11期10卷 1342-1355页

作者： BERGAMASCHI, RA UNIV SOUTHAMPTON DEPT ELECT & COMP SCISOUTHAMPTON SO9 5NHHANTSENGLAND

This paper describes SKOL, a system for the synthesis of combinational logic using a library of cells, with emphasis on the technology mapping algorithms. It combines current multilevel optimization techniques with a new approach to the technology mapping problem. This approach is characterized by the use of a numerical string for representing the Boolean expressions and the library cells, which allows a fast selection process. Technology mapping is performed directly on the factored Boolean network, without decomposing it into primitive gates. A dynamic programming approach is used for mapping the whole Boolean network based on the possible matches for each node. Results from benchmark examples show that this approach is effective in reducing the final cell count. Comparisons with existing systems are presented.

关键词： Libraries Equations Logic arrays Paper technology Logic design Dynamic programming Helium Logic programming Minimization optimizing compilers

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