The complexity of heterogeneous Multi-Processor Systems-on-Chip stretches the limits of software development solutions based on sequential languages such as C/C++. While these are still the most widely used languages ...
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ISBN:
(数字)9783030378738
ISBN:
(纸本)9783030378738;9783030378721
The complexity of heterogeneous Multi-Processor Systems-on-Chip stretches the limits of software development solutions based on sequential languages such as C/C++. While these are still the most widely used languages in practice, model-based solutions appear to be an efficient alternative. However, the optimized compilation of models for multi-processor systems still presents many open research problems. Among others, static data-flow analyses for models require the adaptation of traditional algorithms used in program analysis (iterative and worklist algorithms). These algorithms operate on Control-Flow Graphs with a unique start node (i.e., a node without predecessors) and assume that every basic block is reachable from this start node. In this paper, we present a novel combination of the well-known iterative and worklist algorithms that examines a Control-Flow Graph where basic blocks can be reached by paths that originate from different start states. We apply this solution to functional views of signal and image processing models denoted with uml Activity and sysml Block diagrams. We demonstrate its effectiveness on interval analysis and show that significant reductions in the number of visits of the models' control-flow graphs can be achieved.
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