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A quantitative comparison of parallel computation models

ACM TRANSACTIONS ON COMPUTER SYSTEMS 1998年第3期16卷 271-318页

作者： Juurlink, BHH Wijshoff, HAG Delft Univ Technol Dept Elect Engn Lab Comp Architecture & Digital Tech NL-2628 CD Delft Netherlands Leiden Univ Dept Comp Sci High Performance Comp Div NL-2300 RA Leiden Netherlands

In recent years, a large number of parallel computation models have been proposed to replace the PRAM as the parallel computation model presented to the algorithm designer. Although mostly the theoretical justifications for these models are sound, and many algorithmic results were obtained through these models, little experimentation has been conducted to validate the effectiveness of these models for developing cost-effective algorithms and applications on existing hardware platforms. In this article a first attempt is made to perform a detailed experimental account on the preciseness of these models. To achieve this, three models (BSP, E-BSP, and BPRAM) were selected and validated on five parallel platforms (Cray T3E, Thinking Machines CM-5, Intel Paragon, MasPar MP-1, and Parsytec GCel). The work described in this article consists of three parts. First, the predictive capabilities of the models are investigated. Unlike previous experimental work, which mostly demonstrated a close match between the measured and predicted execution times, this article shows that there are several situations in which the models do not precisely predict the actual runtime behavior of an algorithm implementation. Second, a comparison between the models is provided in order to determine the model that induces the most efficient algorithms. Lastly, the performance achieved by the model-derived algorithms is compared with the performance attained by machine-specific algorithms in order to examine the effectiveness of deriving fast;algorithms through the formalisms of the models.

关键词： parallel computation models performance evaluation

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POLYMORPHIC PROCESSOR ARRAYS

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1993年第5期4卷 490-506页

作者： MARESCA, M INT COMP SCI INST I-16145 GENOAITALY

A Polymorphic Processor Array (PPA) is a two-dimensional mesh-connected array of processors, in which each processor is equipped with a switch able to interconnect its four NEWS ports. PPA is an abstract architecture based upon the experience acquired in the design and in the implementation of a VLSI chip, namely the Polymorphic Torus (PT) chip, and, as a consequence, it only includes capabilities that have been proved to be supported by cost-effective hardware structures. The main claims of PPA are that 1) it models a realistic class of parallel computers, 2) it supports the definition of high level programming models, 3) it supports virtual parallelism and 4) it supports low complexity algorithms in a number of application fields. In this paper we present both the PPA computation model and the PPA programming model;we show that the PPA computation model is realistic by relating it to the design of the PT chip and show that the PPA programming model is scalable by demonstrating that any algorithm having O(p) complexity on a virtual PPA of size square-root m x square-root m, has O(kp) complexity on a PPA of size square-root n x square-root n, with m = kn and k integer. We finally show some application algorithms in the area of numerical analysis and graph processing.

关键词： DATA parallel ALGORITHMS MASSIVELY parallel COMPUTERS MESH CONNECTED COMPUTERS parallel computation models parallel PROGRAMMING models RECONFIGURABLE parallel COMPUTERS SIMD ARCHITECTURES

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Communication primitives for BSP computers

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INFORMATION PROCESSING LETTERS 1996年第6期58卷 303-310页

作者： Juurlink, BHH Wijshoff, HAG High Performance Computing Division Department of Computer Science Leiden University P.O. Box 9512 2300 RA Leiden The Netherlands

The bulk-synchronous parallel (BSP) model is based on two parameters of g and L that characterize the hardware of a machine. A set of communication primitives is studied that have been found useful when implementing scientific and engineering applications. The following problems are considered: 1. single-item broadcast, 2. k-item broadcast, 3. prefix, 4. 2D prefix, 5. sorting P elements, where P is the number of processors, and 6. duplication. The values of g and L that can be obtained in practice depend on: 1. the network topology, 2. the routing algorithm, and 3. technological factors such as the channel capacities and the network cycle time. It is possible to perform a single item broadcast/prefix operation on a P-processor hypercube in O(log P) time. There is a gap of log P/log log P between the network implementation and the BSP implementation. In general, a single communication step of the network model can be simulated on the BSP model in time less than or equal to L.

关键词： parallel algorithms parallel computation models communication operations

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