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Ordered structures for parallel rule-based computations

INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS 2001年第4期78卷 499-520页

作者： Alonso, CL Vela, CR Varela, R Puente, J Univ Oviedo Ctr Inteligencia Artificial Oviedo Spain

In this paper we present an effective strategy to compute a partial order relation among the literals of a query given by a conjuction of first order literals. This ordering expresses sufficient conditions in order for the subgoals of the query were independent each one to the others and hence they can be evaluated in parallel. To represent the partial ordering so that an efficient strategy to join partial solutions from the subgoals can be obtained, we introduce a structure named the Data Flow Lattice. ne problem of determining the optimum partial ordering is proved to be NP-hard, therefore we propose an heuristic algorithm that requires polynomial time in the number of literals and variables of the query. We add also an illustrative example of the algorithm performance.

关键词： parallel logic programming independent AND parallelism Data Flow Lattice

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SEQUENCE CONTROL OF ANALOG-COMPUTERS

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PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON 1972年第10期119卷 1505-&页

作者： BARNEY, GC MILLER, D Research & Development Department Pilkington Brothers Ltd. St. Helens UK Control Systems Centre University of Manchester Institute of Science & Technology Manchester UK

parallel-logic programming of analogue computers often presents difficulties to all but the most experienced users. The paper describes an inexpensive method of simplifying the control of iterative problem solutions run on parallel-logic analogue computers by employing a special-purpose sequence controller. The controller stores up to 16 64 bit words, which are transferred in sequence to an output buffer. Most of the bits within each word form the control signals for analogue components. This is mechanised by connections from the controller-output buffer to the analogue-component control lines via an existing parallel-logic patchboard. Conditional (i.e. comparator-controlled) operations and manual control (using logic switches) are possible with only a limited number of analogue components. A compiler for a digital computer enables the user to define the modes and states of analogue components as a sequence of events in time. These events, and the periods of time between them, may be defined by a list of digital-program-source statements, or, conversationally, by replying to questions typed at the user's teleprinter. Either form of input is compiled into the sequence-controller machine code, which is then loaded into the controller memory ready for execution.

关键词： controllers parallel logic programming iterative problem solutions analogue computers sequence controller Analogue and hybrid computers and systems

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CARMEL-2 - A 2ND GENERATION VLSI ARCHITECTURE FOR FLAT CONCURRENT PROLOG

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NEW GENERATION COMPUTING 1990年第2-3期7卷 197-218页

作者： HARSAT, A GINOSAR, R TECHNION ISRAEL INST TECHNOL DEPT COMP SCIIL-32000 HAIFAISRAEL

CARMEL-2 is a high performance VLSI uniprocessor, tuned forFlat Concurrent Prolog (FCP). CARMEL-2 shows almost 5-fold speedup over its predecessor, CARMEL-1, and it achieves 2,400 KLIPS executingappend. This high execution rate was gained as a result of an optimized design, based on an extensive architecture-oriented execution analysis of FCP, and the lessons learned with CARMEL-1. CARMEL-2 is a RISC processor in its character and performance. The instruction set includes only 29 carefully selected instructions. The 10 special instructions, the prudent implementation and pipeline scheme, as well as sophisticated mechanisms such as intelligent dereference, distinguish CARMEL-2 as a RISC processor for FCP.

关键词： Architecture-Oriented Execution Analysis Flat Concurrent Prolog Intelligent Dereference Modified Memory Interleaving parallel logic programming RISC Single-Cycle Execution Tagged Architecture VLSI

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AN ABSTRACT MACHINE FOR THE IMPLEMENTATION OF PARLOG ON UNIPROCESSORS

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NEW GENERATION COMPUTING 1989年第4期6卷 389-420页

作者： GREGORY, S FOSTER, IT BURT, AD RINGWOOD, GA 1. PARLOG Group Department of Computing Imperial College 180 Queen’s Gate SW7 2BZ London England

An abstract machine that supports the parallel logic programming language PARLOG is presented. This abstract machine is designed for the efficient execution of PARLOG on conventional uniprocessors and is thus named the Sequential PARLOG Machine (SPM). The machine’s architecture and instruction set are described and the principles of compilation of PARLOG programs to sequences of abstract machine instructions explained. The machine supports systems programming in PARLOG and in particular PARLOG’s powerful control metacall, which permits programs to initiate, monitor and control subcomputations.

关键词： PARLOG parallel logic programming Implementation Abstract Machines

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A parallel Bottom-Up Resolution Algorithm Using Cilk

A Parallel Bottom-Up Resolution Algorithm Using Cilk

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25th IEEE International Conference on Tools with Artificial Intelligence (ICTAI)

作者： Basseda, Reza Chowdhury, Rezaul Alam SUNY Stony Brook Dept Comp Sci Stony Brook NY 11794 USA

ISBN: (纸本)9781479929719

Rapid developments of multicore processors in the last ten years have accelerated the advancements in concurrency platforms. Performance of bottom-up resolution algorithms used in logic programming and artificial intelligent systems, can potentially be improved using the parallel programming constructs offered by these platforms (e.g., OpenMP, Cilk++, etc.). In this work we use cilk++ to implement a parallel bottom-up resolution algorithm, and study how different parallel programming constructs affect its performance. Our experimental results show that a careful cilk++ implementation of the algorithm can lead to significant speedup w.r.t. its traditional serial implementation.

关键词： parallel logic programming parallel Resolution Algorithm Bottom-up Reasoning

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NEGATION IN CONCLOG 1st

NEGATION IN CONCLOG

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1ST INTERNATIONAL CONF ON parallel COMPUTATION

作者： JACQUET, JM CTR MATH & COMP SCI 1009 AB AMSTERDAMNETHERLANDS

ISBN: (纸本)9783540554370

This paper presents a new constructive form of the negation-as-failure rule dedicated to concurrent executions and, based on it, a parallel execution model of general Horn clauses. Referring to the completion understanding of the programs, this model has been proved sound and as complete as possible when the resolution rule and the negation-as-failure rule are used. Furthermore, it does not suffer from the floundering problem : in contrast, negative literals can be used to produce computed answers as the positive literals can. This new form of negation is based on an equational framework. It introduces generalizations of substitutions, terms and related concepts of instantiation and unification. A theory of such concepts is also presented in the paper.

关键词： CONSTRUCTIVE NEGATION parallel logic programming parallel LANGUAGE THEORY OF SUBSTITUTIONS AND TERMS

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Nested parallel call optimization

Nested parallel call optimization

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10th International parallel Processing Symposium (IPPS 96)

作者： Pontelli, E Gupta, G NEW MEXICO STATE UNIV LAB LOG DATABASES & ADV PROGRAMMINGLAS CRUCESNM 88003

ISBN: (纸本)0818672552

We present a novel optimization called Last parallel Call Optimization (LPCO) for parallel systems. The last parallel call optimization can be regarded as a parallel extension of last call optimization found in sequential systems. While the LPCO is fairly general, we use and-parallel logic programming systems to illustrate it and to report its performance on multiprocessor systems. The last parallel call optimization leads to improved time and space performance for a majority of and-parallel programs. We also present a generalization of the Last parallel Call Optimization called Nested parallel Call Optimization (NPCO). A major advantage of LPCO and NPCO is that parallel systems designed for exploiting control parallelism can automatically exploit data parallelism efficiently.

关键词： implementation optimizations parallel logic programming and-parallelism

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A TECHNIQUE FOR RECURSIVE INVARIANCE DETECTION AND SELECTIVE PROGRAM SPECIALIZATION 3rd

A TECHNIQUE FOR RECURSIVE INVARIANCE DETECTION AND SELECTIVE...

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3RD INTERNATIONAL SYMP ON programming LANGUAGE IMPLEMENTATION AND logic programming ( PLILP 91 )

作者： GIANNOTTI, F HERMENEGILDO, M CNUCE-CNR Via Santa Maria 36 Pisa 56100 Italy Univ. Politécnica de Madrid (UPM) Facultad de Informática Boadilla del Monte 28660 Madrid Spain

ISBN: (纸本)3540544445

This paper presents a technique for achieving a class of optimizations related to the reduction of checks within cycles. The technique uses both Program Transformation and Abstract Interpretation. After a first pass of an abstract interpreter which detects simple invariants, program transformation is used to build a hypothetical situation that simplifies some predicates that should be executed within the cycle. This transformation implements the heuristic hypothesis that once conditional tests hold they may continue doing so recursively. Specialized versions of predicates are generated to detect and exploit those cases in which the invariance may hold. Abstract interpretation is then used again to verify the truth of such hypotheses and confirm the proposed simplification. This allows optimizations that go beyond those possible with only one pass of the abstract interpreter over the original program, as is normally the case. It also allows selective program specialization using a standard abstract interpreter not specifically designed for this purpose, thus simplifying the design of this already complex module of the compiler. In the paper, a class of programs amenable to such optimization is presented, along with some examples and an evaluation of the proposed techniques in some application areas such as floundering detection and reducing run-time tests in automatic logic program parallelization. The analysis of the examples presented has been performed automatically by an implementation of the technique using existing abstract interpretation and program transformation tools. © Springer-Verlag Berlin Heidelberg 1991.

关键词： logic programming ABSTRACT INTERPRETATION PROGRAM TRANSFORMATION PROGRAM SPECIALIZATION parallel logic programming CYCLE INVARIANT DETECTION COMPILE-TIME OPTIMIZATION

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Achieving scalability in parallel tabled logic programs 16

Achieving scalability in parallel tabled logic programs

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16th International parallel and Distributed Processing Symposium, IPDPS 2002

作者： Rocha, R. Silva, F. Costa, V.S. DCC-FC LIACC Universidade do Porto Portugal COPPE Systems Universidade do Rio de Janeiro Brazil

ISBN: (纸本)0769515738

Tabling or memoing is a technique where one stores intermediate answers to a problem so that they can be reused in further calls. Tabling is of interest to logic programming because it addresses some of the most significant weaknesses of Prolog. Namely, it can guarantee termination for programs with the bounded term-size property. Tabled programs exhibit a more complex execution mechanism than traditional Prolog's left-to-right search with backtracking. The reason is that Prolog programs are highly recursive and generate multiple answers. This rather involved execution mechanism requires a more complex implementation than traditional Prolog. The declarative nature of tabled logic programming suggests that it might be amenable to parallel execution. On the other hand, the complexity of the tabling mechanism, and the existence of a shared resource, the table, argues that parallelism might be limited, and that performance for real applications might never scale. In this work we prove that parallel tabling is indeed scalable for real applications by experimenting the OPTYap parallel tabled system on a scalable shared-memory machine. © 2002 IEEE.

关键词： parallel logic programming Tabling

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A DATA-DRIVEN MODEL FOR A SUBSET OF logic programming

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ACM TRANSACTIONS ON programming LANGUAGES AND SYSTEMS 1987年第4期9卷 618-645页

作者： BIC, L LEE, C Univ. of California Irvine Univ. of California Irvine

There is a direct correspondence between semantic networks and a subset of logic programs, restricted only to binary predicates. The advantage of the latter is that it can describe not only the nodes and arcs comprising a semantic net, but also the data-retrieval operations applied to such nets. The main objective of this paper is to present a data-driven model of computation that permits this subset of logic programs to be executed on a highly parallel computer architecture. We demonstrate how logic programs may be converted into collections of data-flow graphs in which resolution is viewed as a process of finding matches between certain graph templates and portions of the data-flow graphs. This graph fitting process is carried out by messages propagating asynchronously through the data-flow graph; thus computation is entirely data driven, without the need for any centralized control and centralized memory. This permits a potentially large number of independent processing elements to cooperate in solving a given query.

关键词： Data-driven computation parallel logic programming

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