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2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014

作者： Shi, Cong Yang, Jie Han, Ye Cao, Zhongxiang Qin, Qi Liu, Liyuan Wu, Nan-Jian Wang, Zhihua Chinese Academy of Sciences Beijing China Tsinghua University Beijing China

A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing. © 2014 IEEE.

关键词： high-speed techniques image processing image sensors neural nets parallel processing pe array dynamically reconfigurable hybrid architecture high-speed compact vision system image sensor parallel image processors pixel-parallel processors row-parallel SIMD array processors self-organizing map neural network single silicon die vision chip arrays Face recognition Image processing Neural networks Neurons Program processors Solid state circuits

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Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation

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MICROMACHINES 2021年第11期12卷 1365-1365页

作者： Cheng, Wei-Kai Liu, Xiang-Yi Wu, Hsin-Tzu Pai, Hsin-Yi Chung, Po-Yao Chung Yuan Christian Univ Dept Informat & Comp Engn Taoyuan 32023 Taiwan

Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (pe array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of pe array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.

关键词： CNN DRAM pe array dataflow data migration data reuse

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Research of pe array Connection Network for Cool Mega-array

Research of PE Array Connection Network for Cool Mega-Array

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IEEE 27th International Conference on Advanced Information Networking and Applications Workshops (WAINA)

作者： Uno, Rie Ozaki, Nobuaki Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa 223 Japan

ISBN: (纸本)9780769549521;9781467362399

A Cool Mega array or CMA is a low power reconfigurable processor array for battery driven mobile devices. We developed a prototype chip CMA-1. It is consisting of the 8 x 8 pe array, mu-controller for controlling data alignment and data memory. We just borrowed the pe array network of a dynamically reconfigurable processor for the CMA-1, and sufficient examination about it has not been carried out so far. The overhead of the configuration data transfer time to the CMA-1 also appeared to bottleneck the system performance. It means that the quantity of configuration data for the pe array should be as small as possible. In this paper, we proposed and evaluated three types of the CMA which pe array networks are different respectively in order to clarify the pe array network which is the most suitable for the CMA. As a result, in the CMA-const which has island-style interconnection and dedicated links for sending constants, we could reduce the number of steps for transferring configuration data by 44.4% on average, 53.8% at most without a negative influence on performance and power consumption of the CMA.

关键词： reconfigurable system Cool Mega-arrays pe array interconnection low power

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Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

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Science China(Information Sciences) 2014年第10期57卷 170-187页

作者： LIU LeiBo WANG YanSheng YIN ShouYi ZHU Min WANG Xing WEI ShaoJun Institute of Microelectronics Tsinghua University National Laboratory for Information Science and Technology Tsinghua University

Using the coarser operand grain and simplified interconnection patterns, CGRA(coarse grained reconfigurable architectures) has been proven to be energy efficient in several specific domains. As we know, the speed at which the contexts are applied to a peA(processing element array) directly determines the performance of CGRA. In this paper, the design space in CGRA is further developed from the configuration granularity perspective by one middle-grained configuration granularity—the row-based configuration mechanism(RCM).The most prominent feature of the RCM is that a large DFG(data flow graph) can be mapped onto a small array in once reconfiguration, which is carried out on a row-by-row basis. Compared with an ordinary DFGpartitioning solution, the reconfiguration time and the data transfer time are well reduced. Furthermore, the proposed RCM offers much more efficient storage for the contexts. Compared with the DFG partitioning solution,the performance is boosted from 2.6% to 57.8%, while the area penalty is only 4.79% and the power penalty is only 7.22%. The RCM has been used in one reconfigurable processor called REMUS HPA(reconfigurable multi-media system, high performance version advanced). REMUS HPA has been implemented on a 50.5 mm2 silicon with TSMC 65 nm technology. Simulation shows that 1920×1088@37 fps can be achieved for H.264high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP(one commercial reconfigurable processor), the performance is 247% boosted.

关键词： row-based configuration pe array fast reconfiguration context compression DFG portioning

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A High-Speed Vision Processor based on Pixel-Parallel pe array and Its Applications

A High-Speed Vision Processor based on Pixel-Parallel PE Arr...

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2010 IEEE Youth Conference on Information,Computing and Telecommunications(2010 IEEE青年信息、计算和通信技术大会)

作者： Cong Shi Nanjian Wu Zhihua Wang Department of Electronic Engineering Tsinghua University Beijing 100083 China Institute of Semico Institute of Semiconductors Chinese Academy of Sciences Beijing 100083 China Department of Electronic Engineering Tsinghua University Beijing 100083 China

This paper proposes a novel high-speed vision processor based on pixel-parallel pe array. The processor consists of a pixel-parallel pe array, an embedded RISC core, an AHB bus, some SRAM blocks and other logical controllers. pe array performs the low- and mid-level vision processing, and RISC core carries out the high-level vision processing in succession. The vision processor can process vision information at a speed higher than 1000fps. Many application algorithms can be implemented by software programming on the vision processor. The processor prototype is implemented on a FPGA board with a 64×64 pe array and the clock frequency is 100MHz. It can realize moving detection in 128×128 image data at a rate of 4500fps, and 104fps in complicated face detection task for 160×120 video frame sequence. The results demonstrated that the vision processor outperforms the general serial CPUs for more than 60 times.

关键词： High-Speed Vision Processor pe array Moving Detection Face Detection

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One Dimensional SIMD array Processor with Segmentable Bus

One Dimensional SIMD Array Processor with Segmentable Bus

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International Conference on Advanced in Control Engineering and Information Science (CEIS)

作者： Zhang, Fa-cun Liu, Wei Wang, Qian-kun Xian Univ Technol Sch Comp Sci & Engn Xian Peoples R China

By the analysis of the application requirement and the architectures of parallel computer, an embedded data parallel computer architecture model is proposed for multimedia processing applications. In the proposed model, local memory based on PIM technology reduces memory latency and increases bandwidth. Additionally, segmentable bus provides high flexibility for different demands so that pes can cooperate with each other more efficiently. The main components and the instruction set were described in detail. A typical algorithm example is given to show the process of parallel computation. And we are implementing this model under Xilinx FPGA board. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]

关键词： SIMD PIM Data Parallel Computer Architecture Segmentable Bus pe array Instruction Set Architecture

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One Dimensional SIMD array Processor with Segmentable Bus

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Procedia Engineering 2011年 15卷 3704-3709页

作者： Fa-cun Zhang Wei Liu Qian-kun Wang School of Computer Science and Engineering Xi’an University of Technology Xi’an and Shaanxi China

关键词： SIMD PIM Data Parallel Computer Architecture Segmentable Bus pe array Instruction Set Architecture

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A fast VLSI architecture for full-search variable block size motion estimation in MpeG-4 AVC/H.264 05

A fast VLSI architecture for full-search variable block size...

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10th Asia and South Pacific Design Automation Conference

作者： Kim, Minho Hwang, Ingu Chae, Soo-Ik Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea

ISBN: (纸本)0780387368

We describe a fast VLSI architecture for full-search motion ciiation for the blocks with 7 different sizes in MpeG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16x16 pe array, an adder tree and comparators to find all 41 motion vectors and their minimum SADs for the blocks of 16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4. It employs a 2-D datapath and its control of the search area data is simple and regular. The proposed VBSME can achieve 100% pe utilization by employing a preload register and a search data buffer inside each pe and allow real-time processing of 4CIF(704x576) video with 15 fps at 100 Mhz for a search range of [-32 similar to+31].

关键词： VLSI motion estimation video coding integrated circuit design code standards VLSI architecture full-search motion estimation variable block size motion estimation MpeG-4 AVC/H.264 pe array adder tree comparator motion vector 2D datapath preload register search data buffer real-time processing 4CIF video 100 MHz

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