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IEEE Workshop on Signal Processing Systems Design and Implementation

作者： Engin, N Philips Res Labs Eindhoven Netherlands

ISBN: (纸本)0780385047

A scalable, programmable turbo decoder architecture is presented in this paper. The starting point is a comparison of the existing techniques on basis of scalability, area and power consumption. The results from these comparisons lead to a hybrid technique on which our architecture concept is based. The architecture is consisting of clusters each of which is a VLIW architecture. The upsizing is possible by adding a cluster and dividing the two data memories in banks. The window size is chosen according to the number of banks to prevent the conflicts. At the end of the paper, a short evaluation of the architecture is presented.

关键词： iterative decoding convolutional codes maximum likelihood decoding turbo codes parallel architectures programmable circuits convolutional decoders MAP decoder turbo decoder architecture scalable parallelism programmable turbo decoder scalability VLIW architecture clusters data memory banks data window size Iterative decoding Scalability programmable circuits Window Size maximum likelihood decoding Parallel architectures convolutional coding turbo codes ARCHITECTURE Building construction VLIW architecture Turbo Worm gears decoders

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Pure CMOS one-time programmable memory using gate-ox anti-fuse

Pure CMOS one-time programmable memory using gate-ox anti-fu...

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IEEE Custom Integrated circuits Conference

作者： Ito, H Namekawa, T Toshiba Co Ltd SoC Res & Dev Ctr Saiwai Ku Kawasaki Kanagawa 2128520 Japan

ISBN: (纸本)0780384954

A pure CMOS one-time programmable (PCOP) memory is developed as electrically programmable nonvolatile memory for general purposes. The memory cell consists of a thin-oxide PMOS transistor, a thick-oxide NMOS barrier transistor and a selection transistor. It is programmed with the dielectric breakdown of the thin gate oxide. A high voltage generator is built-in so as to be programmable after packaging.

关键词： CMOS memory circuits programmable circuits dielectric thin films random-access storage semiconductor device breakdown pure CMOS OTP memory post-packaging one-time programmable memory gate-oxide anti-fuses electrically programmable nonvolatile memory thin-oxide PMOS transistor thick-oxide NMOS barrier transistor selection transistor thin gate oxide dielectric breakdown high voltage generator high voltage generator programmable circuits CMOS memory circuits semiconductor device breakdown dielectric thin films programmable Antifuses immunocytes

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RADAR - Reconfigurable analog and digital array for radiation-hardened circuits

RADAR - Reconfigurable analog and digital array for radiatio...

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IEEE Aerospace Conference

作者： McMurchie, L Sechen, C Univ Washington Dept Elect Engn Seattle WA 98195 USA

ISBN: (纸本)0780381556

Because of their flexibility and reprogrammability, FPGAs have been proposed for many uses in avionics. Existing commercial FPGAs, being fine-grained, are programmable at the bit level, allowing them to be used across a wide range of applications. Compared to an ASIC developed for a specific application, however, such a fine-grained FPGA consumes more power and exhibits higher latency and/or lower throughput. In this paper we describe RADAR - a coarse-grained, programmable, radiation-hardened array that exhibits power and throughput similar to ASICs, yet contains a high degree of programmability. Containing multipliers, adders, SRAMs and a programmable interconnect, RADAR is customized to the DSP domain and targets applications that require low power and high throughput. The degree of radiation hardening in RADAR is a programmable feature, allowing a tradeoff between radiation hardness, throughput, andpower.

关键词： reconfigurable architectures radiation hardening (electronics) low-power electronics programmable circuits network topology mixed analogue-digital integrated circuits reconfigurable analog array reconfigurable digital array radiation hardened circuit reprogrammability FPGAs avionics programmable array programmable interconnect multipliers adders SRAM DSP domain radiation hardness low power throughput Mixed analog digital integrated circuits avionics programmable circuits adders radiation resistance Reconfigurable architectures low-power electronics radar Network topology programmable Throughput

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Implementation and performance of a multi-band transceiver for software defined radio

Implementation and performance of a multi-band transceiver f...

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IEEE Radio and Wireless Conference (RAWCON 2004)

作者： Araki, K Nakagawa, T Kawashima, M Kobayashi, K Akabane, K Shiba, H Hayashi, H NTT Corp NTT Network Innovat Labs Yokosuka Kanagawa 2390847 Japan

ISBN: (纸本)0780384512

There are various mobile communication standards in use worldwide. Software defined radio (SDR), which enables the creation of multi-standard terminals, is the one of the best ways to achieve seamless mobile communications. To realize an SDR mobile terminal, it is necessary to minimize terminal size and power consumption. NTT developed an RF chipset for a multi-band transceiver and a signal processing board using a reconfigurable processor. This paper describes its implementation and the performance of the multi-band RF chipset along with the results of an evaluation of the signal processing unit.

关键词： MMIC amplifiers MMIC mixers oscillators programmable circuits radio communication equipment transceivers

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A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

A DLL-based programmable clock generator using threshold-tri...

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Proceedings of IEEE Asia-Pacific Advanced System Integrated circuits

作者： Hong-Yi Huang Jian-Hong Shen Department of Electronic Engineering Fu-Jen Catholic University Taiwan

In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and output frequency ranges of multiply-by-1/2/3/6 clock generator at 1.8V supply voltage are 138 MHz /spl sim/ 277MHz and 138 MHz /spl sim/ 1.6GHz, respectively.

关键词： Clocks Jitter Voltage control Delay effects MOS capacitors Frequency Delay lines programmable circuits Voltage-controlled oscillators Threshold voltage

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An architecture for a configurable mixed-signal device

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IEEE JOURNAL OF SOLID-STATE circuits 2003年第3期38卷 565-568页

作者： Mar, M Sullam, B Blom, E Cypress Microsyst Inc Bothell WA 98021 USA

The mixed-signal programmable system-on-chip (PSOC) architecture for high-volume low-cost applications is presented. programmable analog, digital, and clocking circuits are combined with flash memory and a microcontroller to provide a platform for single-chip solutions for low-cost consumer applications. Both programmable analog and digital circuits are designed to support a moderate level of abstraction, balancing flexibility against cost and performance. A rough comparison of alternative approaches based on functionality and cost is presented.

关键词： architecture microcontrollers mixed analog-digital integrated circuits programmable analog circuits programmable circuits systems engineering

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Designing a programmable analog signal conditioning circuit without loss of measurement range

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2003年第5期52卷 1482-1487页

作者： Catunda, SYC Naviner, JF Deep, GS Freire, RCS Univ Fed Maranhao Sao Luis Brazil Ecole Natl Super Telecommun Bretagne Paris France Univ Fed Campina Grande Campina Grande Brazil

Programmabte analog signal conditioning circuits can be programmed in the field to permit their use in several applications with a variety of sensors with different output signal characteristics. The digital programming of the gain and dc level shift of a conditioning circuit can affect the measurement resolution and cause a reduction in the range of the measuring system in which it is employed. For a specified maximum acceptable loss in the measurement resolution, a procedure for defining and employing the programming values that guarantees the full measurement range is proposed. The proposed methodology takes into account practical implementation considerations and cart be employed for designing either discrete or integrated circuits.

关键词： analog circuits gain programming measurement system programmable circuits signal conditioning

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GHz programmable counter with low power consumption

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ELECTRONICS LETTERS 2003年第22期39卷 1572-1573页

作者： Do, MA Yu, XP Ma, JG Yeo, KS Wu, R Zhang, QX Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

A high-speed programmable counter with a new reloadable D flip-flop which integrates the programmable function to a true-single-phase-clock (TSPC) D flip-flop is presented. The proposed reloadable D flip-flop is able to operate at higher frequencies with lower power consumption compared to the performance of the existing bitcell. The programmable divide-by-N counter implemented with this reloadable D flip-flop using the Chartered 0.18 mum CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.

关键词： programmable circuits low-power electronics flip-flops CMOS digitalintegrated circuits counting circuits high-speed integrated circuits GHz programmable counter low power consumption high-speed programmable counter reloadable D flip-flop true-single-phaseclock TSPC D flip-flop programmable divide-by-N counter 1P6M Chartered CMOS process frequencydivider frequency synthesis 2 GHz 1.8 V 4.7 mW 0.18 micron

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Behavioral synthesis of field programmable analog array circuits

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第4期7卷 563-604页

作者： Wang, HB Vrudhula, SBK So Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA Univ Arizona Dept Elect & Comp Engn Tucson AZ 85719 USA

This article presents methods to translate a behavioral-level analog description into a Field programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and postplacement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacitor values due to the limited set of allowable values in an FPAA. For the placement and routing step, an efficient method to estimate the circuit performance degradation due to parasitic effects is given. Using performance degradation as the cost function, an algorithm for finding an optimal FPAA placement and routing configuration is given. The efficacy of the methods developed is demonstrated by direct measurements on a set of filters.

关键词： algorithms design programmable circuits analog synthesis

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Design and development of a demonstration platform dedicated to turbo codes

Design and development of a demonstration platform dedicated...

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Midwest Symposium on circuits and Systems (MWSCAS)

作者： C. Jego Electronic Department CNRS TAMCIC GET/ENST de Bretagne France

SOPC, an acronym for the system on a programmable chip, is an interesting technology that enables a system to combine logic elements, memories and one or more processor cores on the same FPGA. A platform dedicated to turbo codes has been developed using this technology. Error correcting codes are one of the solutions available to improve digital communication quality. Currently the iterative process, known as turbo coding, is the most efficient channel coding technique for digital communications

关键词： Turbo codes Field programmable gate arrays programmable circuits Digital communication Hardware AWGN Logic Error correction codes System-on-a-chip Application software

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