检索结果-内蒙古大学图书馆

0.36 V PGA combining single-stage OTA and input negative transconductor for low energy RF receivers

ELECTRONICS LETTERS 2018年第5期54卷 319-320页

作者： Severo, L. Van Noije, W. Fed Univ Pampa Alegrete Campus Alegrete RS Brazil Univ Sao Paulo Polytech Sch Sao Paulo SP Brazil

An ultra-low voltage and ultra-low power programmable gain amplifier (PGA) using a closed-loop single-stage operational transconductance amplifier (OTA) and an input negative transconductor is proposed. The circuits are implemented in a 180 nm CMOS process using two stacked transistors and PMOS bulk forward bias to operate well down to 0.36 V, to be robust to PVT variations and to reach the bandwidth of low energy RF receivers. The PGA measured results at 0.36 V show a programmable voltage gain from 0.2 to 18.4 dB, 15.4 W power dissipation, 0.98 MHz bandwidth and 0.0243 mm(2) area.

关键词： programmable circuits low-power electronics operational amplifiers CMOS digital integrated circuits single-stage OTA input negative transconductor low-energy RF receivers ultralow-voltage programmable gain amplifier ultralow-power PGA closed-loop single-stage operational transconductance amplifier CMOS process two-stacked transistors PMOS bulk forward bias PVT variations power dissipation voltage 0 36 V size 180 nm gain 0 2 dB to 18 4 dB power 15 4 muW bandwidth 0 98 MHz

来源：评论

学校读者我要写书评

暂无评论

Wide-tuning range programmable threshold comparator using capacitive source-voltage shifting

引用

ELECTRONICS LETTERS 2018年第25期54卷 1417-1418页

作者： Martens, E. Hershberg, B. Craninckx, J. IMEC Smart Elect & Applicat Div Leuven Belgium

A comparator circuit with a built-in programmable threshold is proposed. The threshold is embedded by providing different initial source voltages to each of the input transistors. This source-voltage shifting is done by means of a tunable capacitance, which can synthesise a very wide range of initial voltages, even voltages beyond the supply. This results in a power-efficient comparator structure with a very wide programmable tuning range and low decision delay. The inherently small integrating capacitance of the structure allows for high speed operation even when using small device sizes, minimising input capacitance and maximising efficiency. A practical transistor-level implementation is simulated in a standard 16 nm CMOS technology on a 0.8 V supply, with a tuning range of at least +/- 568 mV.

关键词： integrated circuit design comparators (circuits) CMOS digital integrated circuits programmable circuits transistor circuits comparator circuit input transistors source-voltage shifting tunable capacitance power-efficient comparator structure wide programmable tuning range transistor-level implementation wide-tuning range programmable threshold comparator capacitive source-voltage shifting initial source voltages programmable threshold CMOS technology low decision delay size 16 0 nm voltage 0 8 V

来源：评论

学校读者我要写书评

暂无评论

Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection Methods 31

Comparative Analysis of Inference Errors in a Neural Network...

引用

31st Symposium on Integrated circuits and Systems Design (SBCCI)

作者： Benevenuti, Fabio Libano, Fabiano Pouget, Vincent Kastensmidt, Fernanda Lima Rech, Paolo Univ Fed Rio Grande do Sul Inst Informat PGMICRO Porto Alegre RS Brazil Univ Montpellier IES CNRS Montpellier France

ISBN: (纸本)9781538674314

In this paper we explore multiple and complementary approaches to analyze the single event upset susceptibility of a design implemented in Xilinx 28 nm SRAM-based FPGA. We choose as case study a neural network trained for a classification task. The techniques adopted are neutron irradiation, laser and emulated fault injection. These different techniques are complementary in the sense that they can be applied in different levels of the design integration, from the comprehensive but coarse reliability evaluation of the whole design, provided by the irradiation, to the fine grained and focused reliability investigation of individual modules or devices, provided by laser fault injection. Also, results from these different techniques can be compared allowing their use as crosschecking mechanisms.

关键词： Reliability programmable circuits FPGA fault injection

来源：评论

学校读者我要写书评

暂无评论

programmable, switched-capacitor finite impulse response filter realized in CMOS technology for education purposes 22

Programmable, switched-capacitor finite impulse response fil...

引用

Signal Processing - Algorithms, Architectures, Arrangements, and Applications (SPA)

作者： Pawlowski, Pawel Pawlikowski, Adam Dlugosz, Rafal Dabrowski, Adam Poznan Univ Tech Fac Comp Div Signal Proc & Elect Syst Piotrowo 3a PL-60965 Poznan Poland UTP Univ Sci & Technol Fac Telecommun Comp Sci & Elect Engn Kaliskiego 7 PL-85796 Bydgoszcz Poland Apt Poland SA Podgorki Tynieckie 2 PL-30399 Krakow Poland

ISBN: (纸本)9788362065332

The paper reports comprehensive laboratory tests of a mixed analog-digital, application specific integrated circuit (ASIC). The realized chip is a programmable device. It contains such components as an operational amplifier, a sample-and-hold (S&H) element, programmable array of capacitors, multiphase clock generator and a programmable switched capacitor (SC) delay line. All these blocks may be used separately or may be coupled together into a finite impulse response (FIR) filter, with reconfigurable frequency response. Since the filter coefficients may be either positive or negative, therefore both lowpass or highpass frequency responses may be obtained. The chip has been designed in the AMS CMOS 0.35 mu m technology and occupies the area of 0.5mm(2). It was designed for educational purposes. Programming and testing of the chip was made with the computer-controlled interface prepared in the National Instruments LabVIEW environment. The presented solutions allow for conducting of various laboratory exercises.

关键词： Switched capacitor circuits programmable circuits CMOS technology Education

来源：评论

学校读者我要写书评

暂无评论

An Analog Multi-shaped and Fully programmable Twin-cell MFG Structure in 65nm CMOS Technology

An Analog Multi-shaped and Fully Programmable Twin-cell MFG ...

引用

Iranian Conference on Electrical Engineering (ICEE)

作者： Saeed Karami Hossein Ghasemian Ebrahim Abiri Mohammad Reza Salehi Electrical and Electronic Department Shiraz University of Technology Shiraz Iran

In this paper, a novel method to implement an analog fully programmable membership function generator (MFG) architecture with twin-cell MFG is presented which operates in Transconductance-mode, easily. The proposed multi-shaped MFG circuit is capable of producing the Triangular, Trapezoidal, S and Z-shaped. Also, a fully programmability status in all parameters like Width, Height and Position is available. To make this purpose, by changing of the applied input constant voltages and bias current can reach to programming, independently. Therefore, the proposed MFG architecture is suitable for a general purposes fuzzy logic controller (FLC). In this proposed MFG approach only 26 transistors are used, so the chip area and total power consumption can be reduced to 552um 2 and 83.8uW, respectively which are decreased in comparison with the other researches. The proposed MFG circuit is simulated in 65nm standard CMOS technology with a single supply voltage of 1.2V. Post-layout simulation results show that the proposed circuit is in the great agreement which indicates high precision of the proposed design.

关键词： CMOS analog integrated circuits Fuzzy logic Low-power electronics Integrated circuit layout Power demand programmable circuits

来源：评论

学校读者我要写书评

暂无评论

FPGA based point to point Data Transfer System with single clock signal synchronization 38

FPGA based point to point Data Transfer System with single c...

引用

38th IEEE Central America and Panama Convention (CONCAPAN)

作者： Flores, Daniel Univ Nacl Autonoma Honduras Dept Ingn Elect Tegucigalpa Honduras

ISBN: (纸本)9781538661222

To build a point to point data transfer system with a configurable protocol, the FPGA devices are used as a cheaper alternative versus ASIC;especially if every data package must be synchronous with a single clock signal for both receiver and transmitter. A brief description of the desired system, hardware programming that rules the communication protocol, design and fabrication of the printed circuit board that makes possible the communication between two FPGA Mezzanine Card through SCSI cable and the final testing of the system, are the followed steps to perform this flexible and high velocity scientific research oriented system.

关键词： Field programmable gate arrays Printed circuits Data transfer Digital communication programmable circuits

来源：评论

学校读者我要写书评

暂无评论

Low power current-mode analog front-end for biomedical applications 21

Low power current-mode analog front-end for biomedical appli...

引用

21st IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR THETA)

作者： Groza, Robert Farago, Paul Tech Univ Cluj Napoca Fac Elect Telecommun & Informat Technol Bases Elect Dept Cluj Napoca Romania

ISBN: (纸本)9781538622056

Biopotential signals such as Electrocardiogram (ECG), Electromyogram (EMG), Electroencephalogram (EEG), etc. have very small amplitudes and low frequencies. One of the most important component in a biomedical electronic detection system is the biopotential acquisition device. In this paper, a new current-mode analog front-end for biopotential signal acquisition is proposed. It consists of a programmable gain current-mode amplifier (PGC-MA) and a second order current mode low-pass filter (C-MLPF). The implementation of the amplifier and the low-pass filter was done using Externally Linear Internally Nonlinear (ELIN) circuits. The ELIN blocks were implemented using log-domain circuits. Due to this approach, the gain (G) of the PGC-MA, corner frequency (omega(0)), quality factor (Q) and gain (A) of the C-MLPF, can be tuned using some bias currents. To decrease the power consumption, CMOS transistors operating in subthreshold region were used. The basic building blocks were implemented on a 180nm CMOS process. Spice simulations were performed to validate the proposed solution.

关键词： analog front-end biopotential acquisition system ELIN log-domain circuits programmable circuits

来源：评论

学校读者我要写书评

暂无评论

Reliability Evaluation on Interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC 19

Reliability Evaluation on Interfacing with AXI and AXI-S on ...

引用

19th IEEE Latin-American Test Symposium (LATS)

作者： Benevenuti, Fabio Kastensmidt, Fernanda Lima Univ Fed Rio Grande do Sul UFRGS Inst Informat PGMICRO Porto Alegre RS Brazil

ISBN: (纸本)9781538614723

This work is set in the context of fault tolerance and reliability of critical cyber-physical systems (CPS) based on state-of-art commercial off-the-shelf (COTS) SRAM-based FPGA devices and, in special, the all programmable system-onchips (AP-SoC) that are a class of devices combining a general purpose processing system (PS) with custom programmable logic (PL). In SRAM-based FPGAs the Single Event Upsets (SEU) are unavoidable and may alter the contents of storage elements such as flip-flop and, of interest to this work, the configuration memory (CRAM). We analyze the case of Xilinx Zynq-7000, which is based on multi-core ARM processor that, ultimately, provides as one of its major communication interface the ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI). In this context, we analyze reliability of communication interfaces between the embedded processor and the programmable logic and the different hardware modules on each side. For this, we deal with both (1) the development of experimental procedures and tools for fault injection on SRAM-based FPGAs and (2) the development of bottomup reliability models that would allow estimating system level reliability by aggregating individual reliability from the different hardware modules and communication interfaces obtained from those experimental procedures and tools. In this scenario, fault injection contributes with fine grain reliability evaluation of each component module.

关键词： Reliability programmable circuits FPGA fault injection

来源：评论

学校读者我要写书评

暂无评论

programmable analogue circuits with multilevel memristive device

引用

ELECTRONICS LETTERS 2012年第22期48卷 1415-1416页

作者： Park, S. Park, J. Kim, S. Lee, W. Lee, B. H. Hwang, H. Gwangju Inst Sci & Technol Kwangju 500712 South Korea Pohang Univ Sci & Technol Pohang 790784 South Korea

It is demonstrated that a nanoscale multilevel memristive device using titanium oxide can be used to form programmable analogue circuits without an active transistor. A multilevel memristive device enables a high a degree of programmability particularly for analogue applications since it will not introduce any significant parasitic components. Also, the ring oscillator application with the memristive device is merely a demonstrative example of the enabled high programmability.

关键词： programmable controllers programmable circuits ELECTRONIC controllers TRANSISTORS NANOSTRUCTURED materials

来源：评论

学校读者我要写书评

暂无评论

Energy-efficient Reconfigurable FEC Processor for Multi-standard Wireless Communication Systems

引用

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2017年第3期17卷 333-340页

作者： Li, Meng Van der Perre, Liesbet van Thillo, Wim Lee, Youngjoo Interuniv Microelect Ctr IMEC Vzw B-3001 Leuven Belgium Katholieke Univ Leuven Dept Elect Engn B-3001 Leuven Belgium POSTECH Dept Elect Engn Pohang 37673 South Korea

In this paper, we describe HW/SW cooptimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, tasklevel out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

关键词： Digital integrated circuits error correction codes programmable circuits wireless communication

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：