检索结果-内蒙古大学图书馆

Silicon Nanoelectronics Workshop

作者： Wang, Juncheng Du, Gang Liu, Xiaoyan Peking Univ Inst Microelect Beijing 100871 Peoples R China

ISBN: (纸本)9781467376044

Reconfigurable Silicon nanowire Schottky Barrier transistors (RFETs) with configurability to be programmed as n/p-type polarity are promising for future integrated circuits. In this work, the tunable polarity characteristics of RFETs are investigated. TCAD simulations have been performed for RFETs-based INV, NOR, NAND logic gates and SRAM cell. 4-terminal RFETs presented show the potential of programmable circuits and high density integration.

关键词： configurability Logic gates SRAM cells programmable circuits Static random access storage Schottky barriers Nanowire Silicon Electric circuits

来源：评论

学校读者我要写书评

暂无评论

Class of memristors from cascade of static nonlinear two ports with dynamic one-ports

Class of memristors from cascade of static nonlinear two por...

引用

International Joint Conference on Neural Networks (IJCNN)

作者： Alon Ascoli Ronald Tetzlaff Fernando Corinto Faculty of Electronics and Electrotechnics Technische Unlvcrsitat Dresden Dresden Germany Department of Electronics and Telecommunications Politecnico di Torino Torino Italy

A class of memristor circuits is obtained by cascading a static nonlinear two-port with a dynamical one-port. The terminals of the input port of the static nonlinearity represent the access nodes for each memristor in the class. The class may be splitted into two sub-classes, namely the current- and voltagecontrolled memristors. Two further sets of memristors may be identied within each of such sub-classes, particularly the current- and voltage state memristors. The simplest memristor circuits from the proposed class employ solely passive two-terminal elements from circuit theory. This represents an absolute novelty in the panorama of memristor emulators. The passive elements from the class are volatile memories. However, non-volatile memory behaviour may arise in case the dynamical one-port contains active elements. The versatile nature of the circuit topologies of the proposed memristors allows the emergence of a wide variety of complex dynamical behaviours, which may enable the accomplishment of novel signal processing tasks or lead to improvements in the performance of conventional circuits.

关键词： programmable circuits Conductivity Bridge circuits Memristors Integrated circuits

来源：评论

学校读者我要写书评

暂无评论

programmable Optical Packet/Circuit Switched Data Centre Interconnects: Traffic Modeling and Evaluation

Programmable Optical Packet/Circuit Switched Data Centre Int...

引用

European Conference on Optical Communication (ECOC)

作者： Shu, Y. Zervas, G. Yan, Y. Peng, S. Yan, S. Hugues-salas, E. Simeonidou, D. Univ Bristol High Performance Networks Grp Bristol BS8 1TH Avon England

A programmable all-optical data center network architecture with great scalability and flexibility is proposed and evaluated by a statistic data center traffic model to obtain the best utilization efficiency for optic... 详细信息

ISBN: (纸本)9781479930661

关键词： computer centres optical interconnections packet switching programmable circuits traffic flexibility optical packet/circuit switched network programmable all-optical data center network architecture scalability statistic data center traffic model Optical fiber networks Optical fibers Optical packet switching Optical switches Servers

来源：评论

学校读者我要写书评

暂无评论

Formal Verification of Circuit-Switched Network on Chip (NoC) Architectures using SPIN 16

Formal Verification of Circuit-Switched Network on Chip (NoC...

引用

16th International Symposium on System-on-Chip (SoC)

作者： Zaman, Anam Hasan, Osman Natl Univ Sci & Technol Sch Elect Engn & Comp Sci Islamabad Pakistan

ISBN: (纸本)9781479968909

Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification of circuit-switched NoC's, which provide a dedicated channel for all communications with full bandwidth and thus are found to be more efficient than packet-switched NoCs in many contexts. In particular, the paper presents a generic methodology for the formal verification of circuit-switched NoC using the SPIN model checker. The proposed methodology provides generic modelling guidelines and identifies some properties, including deadlock freedom, starvation freedom, mutual exclusion and liveness, that are quite useful in the context of circuit-switched NoC. For illustration purposes, we use our methodology to verify the programmable NoC (PNoC) architecture, which is one of the most widely used circuit-switched NoC.

关键词： formal verification network-on-chip programmable circuits PNoC architecture SPIN model checker circuit-switched NoC deadlock freedom generic modelling guidelines mutual exclusion network on chip architectures packet-switched NoC programmable NoC architecture starvation freedom Computer architecture Data transfer Integrated circuit modeling Model checking Switches Switching circuits System recovery Formal verification network-on-chip system recovery programmable circuits mutual exclusion Switched circuits integrated circuit modelling data transmission Computer Architecture Model checking circuit switching Switches spin model Spin

来源：评论

学校读者我要写书评

暂无评论

Mixed-Signal Power System Emulator Extension to Solve Unbalanced Fault Transient Stability Analysis

Mixed-Signal Power System Emulator Extension to Solve Unbala...

引用

2014 Power Systems Computation Conference (PSCC)

作者： Lanz, Guillaume Kyriakidis, Theodoros Cherkaoui, Rachid Kayal, Maher Ecole Polytech Fed Lausanne Elect Lab CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Power Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9788393580132

This paper presents the extension of a platform originally devoted to symmetrical transient stability analysis, into the domain of unbalanced faults. The aim of this solver is to increase the speed of dynamic stability assessment for power systems. It is based on an analog representation of the grid alongside dedicated digital resources for the simulation of the models of power network components. Using the symmetrical components theory, this platform can be adapted to handle unsymmetrical disturbances, such as single-phase-to-ground faults, and the tripping of single-phase circuit breakers.

关键词： mixed analog digital circuits power system dynamics power system stability programmable circuits

来源：评论

学校读者我要写书评

暂无评论

Design of a 4-bit programmable Delay with TDC-based BIST for Use in Serial Data Links 14

Design of a 4-bit Programmable Delay with TDC-based BIST for...

引用

14 International Symposium on Integrated circuits (ISIC)

作者： Mehrabi, Taha Raahemifar, Kaamran Geurkov, Vadim Ryerson Univ Elect & Comp Engn Dept Toronto ON Canada

ISBN: (纸本)9781479948338

Time mode signal processing (TMSP) in general is defined as the manipulation of sampled analog signal information using time difference variable. TMSP allows one to implement analog signal processing functions using the most basic element available, namely, propagation delay. A time to digital converter (TDC) is used to convert the time difference between two edges of two signals into a sequence of digital numbers. TDCs have been extensively used in designing laser range finders, all digital phase locked loops (ADPLL), frequency synthesizers, analog to digital converters (ADC), SerDes, etc. This paper proposes a new approach that utilizes a TDC for detection of potential stuck-at faults in a 4-bit programmable delay to be used in designing a time mode SerDes. Moreover, the proposed approach suggests that, when any circuit needs to delay a certain signal, it can be confirmed whether the amount of delay is correctly enforced by utilizing a TDC module and translating the difference between the main signal and the delayed version of the signal into a sequence of bits. Then, one can observe if the generated bits correspond to a correct operation of the circuitry in charge of delaying the main signal.

关键词： built-in self test circuit testing delay circuits fault diagnosis programmable circuits signal generators time-digital conversion ADC ADPLL TDC-based BIST TMSP all digital phase locked loop analog signal processing function analog to digital converter frequency synthesizer laser range finder potential stuck-at fault detection programmable delay propagation delay sampled analog signal information serial data link signal sequence time difference variable time mode SerDes time mode signal processing time to digital converter word length 4 bit Integrated circuits analog digital converter Built-in self test laser range finders delay circuits programmable circuits circuit testing frequency synthesizers Signal generators Propagation delay all digital phase-locked loop Signal Peptides Fault diagnosis programmable DELAY TimeDif Transcranial Direct Current Stimulation

来源：评论

学校读者我要写书评

暂无评论

Intelligent environment monitoring system based on Innovative Integration Technology via programmable System On Chip platform and ZigBee network

引用

IET COMMUNICATIONS 2013年第16期7卷 1789-1801页

作者： Sung, Wen-Tsai Hsu, Chia-Cheng Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41170 Taiwan

This work builds an intelligent environmental monitoring system for industrial production and safety concerns. There are a number of smart monitoring systems developed for smart grids, bridges or machine system management, temperature/humidity monitoring and so on. As information technology advances at a continuous rapid pace, humans have become connected online and this connection has extended into the interactions between things and humans. Employing the FLAG-PSoC-1605A development board as the platform, all sensor data are transmitted via a ZigBee wireless module, a TCP/IP network module and a long range wireless communication GPRS/SMS module to a remote end PC for analysis. This constitutes a smart network for connections between humans and objects.

关键词： cellular radio computerised monitoring electronic messaging microcomputers packet radio networks programmable circuits radio transmitters system-on-chip transport protocols wireless sensor networks Zigbee environmental monitoring (geophysics) remote end PC long range wireless communication GPRS-SMS module TCP-IP network module ZigBee wireless module network sensor data transmission FLAG-PSoC-1605A development board information technology temperature-humidity monitoring machine system management bridge smart grid smart monitoring network system safety concern industrial production programmable system on chip platform innovative integration technology intelligent environment monitoring system

来源：评论

学校读者我要写书评

暂无评论

Mismatch Characterization and Calibration for Accurate and Automated Analog Design

引用

IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2013年第3期60卷 548-556页

作者： Shapero, Samuel Hasler, Paul Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

Device mismatch has long prevented the implementation of accurate high density analog computation. This paper presents the Reconfigurable Analog Signal Processor (RASP) 2.9a, a 350 nm double-poly CMOS chip designed for the implementation of accurate analog computation. The chip is the densest field programmable analog array (FPAA) to date, containing over 130 k programmable floating gate switch elements (SWEs). The paper reviews an algorithm for rapidly programming the charge on floating gate switch elements with 10.2 bit accuracy. An automated algorithm based on the EKV transistor model is developed to rapidly characterize device mismatch, the Early effect, capacitive drain coupling, and temperature dependent behavior. This paper empirically verifies the characterization, using the precise floating gate programming methods to offset the errors and create current sources with 2.2% RMS error over a dynamic range of 25 dB. The current sources are then modified to create current mirrors and vector-matrix multipliers, accurate for currents down to 8 nA. Together with the computational analog blocks, these linear circuits can be synthesized into a wide range of extremely low power linear and nonlinear functions. The calibration routine, in combination with preexisting design tools, allows the automated synthesis, placement, and accurate programming of large classes of circuits on an FPAA.

关键词： Circuit tuning compensation current mode circuits linear network synthesis programmable circuits

来源：评论

学校读者我要写书评

暂无评论

programmable CMOS/Memristor Threshold Logic

引用

IEEE TRANSACTIONS ON NANOTECHNOLOGY 2013年第2期12卷 115-119页

作者： Gao, Ligang Alibart, Fabien Strukov, Dmitri B. Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

This paper proposes a hybrid CMOS/memristor implementation of a programmable threshold logic gate. In this gate, memristive devices implement ratioed diode-resistor logic, while CMOS circuitry is used for signal amplification and inversion. Due to the excellent scaling prospects and nonvolatile analog memory of memristive devices, the proposed threshold logic is in-field configurable and potentially very compact. The concept is experimentally verified by implementing a 4-input symmetric linear threshold gate with an integrated circuit CMOS flip-flop, silicon diodes, and Ag/a-Si/Pt memristive devices.

关键词： Memristor neural networks programmable circuits solid-state electrolyte memory threshold logic

来源：评论

学校读者我要写书评

暂无评论

Controlling the Polarity of Silicon Nanowire Transistors

引用

SCIENCE 2013年第6139期340卷 1414-1415页

作者： Ernst, Thomas CEA LETI MINATEC F-38054 Grenoble France

Each generation of integrated circuit (IC) technology has led to new applications. The most recent advances have enabled noninvasive surgery, three-dimensional (3D) games and movies, and intelligent cars, to name a few. A single chip can contain more than 1 billon elementary devices, and this gain in complexity has been achieved by fabricating nanometer-scale transistors used as switches or memories. Recent experimental work by De Marchi et al. (1) describes changes to the structure of one of the most basic bricks of ICs by controlling the type of conduction occurring in vertically stacked silicon (Si) nanowire transistors (see the figure, panels A and B), thus making a programmable transistor.

关键词： LOGIC circuits INTEGRATED circuits POLARITY (Physics) HOLES (Electron deficiencies) CHARGE carriers (Nuclear physics) ELECTRONS CMOS integrated circuits SILICON nanowires programmable circuits TRANSISTORS

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：