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Leveraging Memristive Systems in the Construction of Digital Logic circuits

PROCEEDINGS OF THE IEEE 2012年第6期100卷 2033-2049页

作者： Rose, Garrett S. Rajendran, Jeyavijayan Manem, Harika Karri, Ramesh Pino, Robinson E. USAF Res Lab Informat Directorate Rome NY 13441 USA Polytech Inst New York Univ Dept Elect & Comp Engn Brooklyn NY 11201 USA

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

关键词： Digital integrated circuits memristors nanoelectronics programmable circuits

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Mapping of Image and Network Processing Tasks on High-Throughput CMOL FPGA circuits 20

Mapping of Image and Network Processing Tasks on High-Throug...

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20th IFIP/IEEE International conference on Very Large Scale Integration (VLSI-SoC)

作者： Madhavan, Advait Strukov, Dmitri B. Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

ISBN: (纸本)9781467326582

A simple two-terminal memristive device has excellent scaling properties. For example, devices with footprint below 10x10 nm(2) have been recently demonstrated and crossbar structures provide means of sustaining memristor density in large-scale circuits. While taking advantage of high density memristive devices is relatively straightforward in crossbar memory circuits, doing so efficiently in digital logic circuits still remains challenging. For example, only a small fraction (less than 1% on average) of memristive devices is actively utilized, i.e. turned to highly conductive state, in CMOL FPGA circuits which are configured to implement representative benchmark circuits. The main contribution of this paper is to demonstrate that such utilization can be much higher, more than 12%, in certain variety of CMOL FPGA circuits which are specifically designed for high throughput processing of streaming data. The high memristor device utilization is demonstrated by performing detailed mapping of network and image processing tasks and is mainly due to efficient use of high fan-in logic gates implementing exact and approximate pattern matching operations with streaming data. As a result of high utilization proposed circuits are estimated to have much higher computational throughput as compared to traditional approaches and represent a killer application which capitalizes efficiently on the density advantages of memristive devices.

关键词： Memristor programmable circuits Hybrid circuits Image Processing Network Processing CMOL FPGA

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Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures

Formic: Cost-efficient and Scalable Prototyping of Manycore ...

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20th IEEE International Symposium on Field-programmable Custom Computing Machines (FCCM)

作者： Lyberis, Spyros Kalokerinos, George Lygerakis, Michalis Papaefstathiou, Vassilis Tsaliagkos, Dimitris Katevenis, Manolis Pnevmatikatos, Dionisios Nikolopoulos, Dimitris Fdn Res & Technol FORTH ICS Inst Comp Sci Iraklion Crete Greece

ISBN: (纸本)9780769546995

Modeling emerging multicore architectures is challenging and imposes a tradeoff between simulation speed and accuracy. An effective practice that balances both targets well is to map the target architecture on FPGA platforms. We find that accurate prototyping of hundreds of cores on existing FPGA boards faces at least one of the following problems: (i) limited fast memory resources (SRAM) to model caches, (ii) insufficient inter-board connectivity for scaling the design or (iii) the board is too expensive. We address these shortcomings by designing a new FPGA board for multicore architecture prototyping, which explicitly targets scalability and cost-efficiency. Formic has a 35% bigger FPGA, three times more SRAM, four times more links and costs at most half as much when compared to the popular Xilinx XUPV5 prototyping platform. We build and test a 64-board system by developing a 512-core, MicroBlaze-based, non-coherent hardware prototype with DMA capabilities, with full network-on-chip in a 3D-mesh topology. We believe that Formic offers significant advantages over existing academic and commercial platforms that can facilitate hardware prototyping for future manycore architectures.

关键词： programmable circuits prototypes multicore processing design methodology

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programmable LPF-based Stator Flux Estimator for Sensorless Induction Motor Control

Programmable LPF-based Stator Flux Estimator for Sensorless ...

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IEEE Vehicle Power and Propulsion Conference (VPPC)

作者： Lee, Sang-Soo Kim, Jae-Hoon Hyun, Dong-Seok Hanyang Univ Dept Elect Engn Seoul South Korea

ISBN: (纸本)9781467309547

In this paper, the improved stator flux estimator is proposed to ensure a programmable low pass filter (PLPF) to act as a pure integrator for sensorless control of induction motor. The estimated synchronous angular speed is used as a pole of a PLPF whose gain and phase compensator is determined on the assumption of the estimated synchronous angular speed being coincident with the actual one. However, if the synchronous angular speed is not exactly estimated, the gain and phase compensation will not be appropriate. To overcome the mentioned problem, this paper analyzes the relation between the synchronous speed error and the phase lag error of the stator flux. Based on the analysis, the synchronous speed error compensation scheme is proposed. For a sensorless start-up, this paper utilizes the current model as a flux estimator at the standstill. When the current model is switched to the voltage model, large fluctuations in the stator flux and the motor speed can be caused. Therefore, the simple method for a smooth transition between two models is proposed. Validity of the proposed schemes is verified through both simulation results and experimental results.

关键词： angular velocity control electric current control induction motors integrating circuits low-pass filters programmable circuits sensorless machine control

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A Novel Fast Digital Control DC-DC Converter

A Novel Fast Digital Control DC-DC Converter

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IEEE Vehicle Power and Propulsion Conference (VPPC)

作者： Kurokawa, Fujio Tamenaga, Haruki Komichi, Yoshihiko Yamabe, Yoshihiko Shibata, Yuichiro Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781467309547

This paper presents a performance characteristic of a novel fast digital control dc-dc converter. It is able to detect the peak point of the reactor current at real time. The proposed circuit configuration is very easy. It is composed of a very low cost Voltage Controlled Oscillator (VCO), the programmable delay circuit and a few flip-flops. It is confirmed the main switch is turned off when the peak reactor current is detected. Furthermore it is shown that the proposed method has the superior transient response to control dc-dc converters. As a result, the undershoot of output voltage is suppressed to 28% compared with the conventional method's one. The convergence time is also improved to 76% compared with the conventional method's one.

关键词： DC-DC power convertors delay circuits digital control flip-flops programmable circuits transient response voltage-controlled oscillators

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Universal programmable quantum circuit schemes to emulate an operator

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JOURNAL OF CHEMICAL PHYSICS 2012年第23期137卷 234112-234112页

作者： Daskin, Anmer Grama, Ananth Kollias, Giorgos Kais, Sabre Purdue Univ Dept Chem Dept Phys W Lafayette IN 47907 USA Purdue Univ Birck Nanotechnol Ctr W Lafayette IN 47907 USA Qatar Environm & Energy Res Inst Doha Qatar Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system;present the evolution operator U = e-iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule. (C) 2012 American Institute of Physics. [http://***/10.1063/1.4772185]

关键词： eigenvalues and eigenfunctions hydrogen matrix algebra phase estimation programmable circuits quantum chemistry quantum gates wave functions

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Standard-Based Approach to programmable Hybrid Networks

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IEEE COMMUNICATIONS MAGAZINE 2011年第5期49卷 148-155页

作者： Cafini, Raul Cerroni, Walter Raffaelli, Carla Savi, Michele DEIS Univ Bologna Bologna Italy

programmable hybrid networks are considered in this article as a challenge to deploy flexible solutions for next-generation networks. A modular programmable router architecture, which takes advantage of emerging standards, is proposed to support dynamic management and configuration capabilities of network resources and services. The new node design concepts allow vendor-independent development of hybrid router functionalities and possible investigation of new standard interfaces. Validation of the proposed approach is proven in an open source software router context, emulating a hybrid circuit/packet service based on optical switching technology. The software emulator obtained allows programmable hybrid router functionalities to be tested at different levels of abstraction and with different modeling granularities, and is able to represent both logical and physical aspects.

关键词： Hybrid integrated circuits IP networks Network topology Optical switches programmable circuits

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Low-power programmable divider with a shared counter for frequency synthesiser

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IET circuits DEVICES & SYSTEMS 2011年第3期5卷 170-176页

作者： Kim, K. -Y. Min, Y. -J. Kim, S. -W. Park, J. Korea Univ Sch Elect Engn 15 Ka Seoul 136713 South Korea

A low-power programmable divider (PD) for frequency synthesiser is presented in this study. Instead of two counters used in conventional PD, a shared counter with a small control circuit is exploited in order to reduce the output load capacitance and the redundant counter operations in the divider. A novel glitchless D flip-flop is also proposed by considering the switching activities of the internal nodes of the flip-flop. The authors' proposed PD was fabricated in a standard 0.18-mu m complementary metal-oxide-semiconductor (CMOS) technology. The average power is 3.23 mW with 1.5 V supply voltage and the effective area is 0.0408 mm(2). Its division ratio ranges from 13 to 1278 at 3.5 GHz. Experimental results show that the proposed divider consumes around 30% less power compared to the conventional design.

关键词： load capacitance programmable circuits redundant counter operations voltage 1.5 V division ratio size 0.18 mum control circuit flip-flops low-power programmable divider shared counter glitchless D flip-flop CMOS technology PD fabrication counting circuits frequency 3.5 GHz CMOS integrated circuits frequency synthesiser frequency synthesizers

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A Monolithic programmable Nerve/Muscle Stimulator

A Monolithic Programmable Nerve/Muscle Stimulator

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5th International IEEE Engineering-in-Medicine-and-Biology-Society (EMBS) Conference on Neural Engineering (NER)

作者： Tan, Jason Yi Jun Liu, Xu Wee, Keng Hoong Yen, Shih-Cheng Xu, Yong Ping Tan, Ter Chyan Natl Univ Singapore Dept Elect & Comp Engn Singapore Singapore Natl Univ Hlth Syst Dept Hand & Reconstruct Microsurg Singapore Singapore

ISBN: (纸本)9781424441419

This paper presents a monolithic single-channel programmable nerve/muscle stimulator implemented in a 0.35 mu m CMOS technology. It consists of a 10-bit current output digital-to-analog converter (DAC) to generate the required cathodic and anodic currents, and a simple digital circuit to control the operation of the stimulator and its programmable stimulation parameters. The proposed stimulator produces balanced biphasic current pulses, with programmable amplitude, frequency and pulse width. The experimental results show that the stimulator can provide cathodic current with amplitudes ranging from 10 mu A to 10mA, and adjustable pulse widths from 8 mu s to 120 mu s at a clock of 125kHz. The amplitude of the anodic currents designed to be half of the cathodic current to facilitate charge balance. The measured charge mismatch is less than 63nC.

关键词： Animals CMOS integrated circuits CMOS technology Clocks Current measurement Delay Electrodes Muscles Radiation detectors anodic currents bioelectric phenomena biphasic current pulses cathodic currents charge balance charge mismatch current 10 muA to 10 mA digital circuit digital-analogue conversion digital-to-analog converter frequency 125 kHz monolithic integrated circuits monolithic programmable nerve-muscle stimulator muscle neurophysiology patient treatment programmable circuits programmable stimulation parameters size 0.35 mum time 8 mus to 120 mus

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BACKUS LANGUAGE FOR FUNCTIONAL NANO-DEVICES

BACKUS LANGUAGE FOR FUNCTIONAL NANO-DEVICES

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34th International Semiconductor Conference (CAS)

作者： Malita, Mihaela Stefan, Gheorghe M. St Anselm Coll Manchester NH USA Univ Politehn Bucuresti Bucharest Romania

ISBN: (纸本)9781612841717

The emergent nano-technologies must be used to design functional nano-devices with complexity in the range of their size. The way to achieve this goal is to define parallel programmable engines. The concept of FP System, introduced by John Backus in 1978, is used to define a high level architectural environment: Backus-Connex Parallel Functional Programming System. The functional forms of FP Systems correspond perfect with the four types of parallelism derived for ConnexArray (TM) from the Kleene's computational model. The paper defines the BC programming environment, describes its implementation in Scheme and presents its use for developing real applications for functional nano-devices.

关键词： nano-electronics functional electronics programmable circuits parallelism functional programming

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