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An ultrafast quantum random number generator with provably bounded output bias based on photon arrival time measurements

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APPLIED PHYSICS LETTERS 2011年第17期98卷 171105-171105页

作者： Wahl, Michael Leifgen, Matthias Berlin, Michael Roehlicke, Tino Rahn, Hans-Juergen Benson, Oliver PicoQuant GmbH D-12489 Berlin Germany Humboldt Univ Inst Phys D-12489 Berlin Germany

We report the implementation of a quantum random number generator based on photon arrival times. Due to fast and high resolution timing we are able to generate the highest bitrate of any current generator based on photon arrival times. Bias in the raw data due to the exponential distribution of the arrival times is removed by postprocessing which is directly integrated in the field programmable logic of the timing electronics. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3578456]

关键词： light emitting diodes logic circuits photomultipliers programmable circuits quantum optics random number generation

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An Integration Technology for RF and Microwave circuits Based on Interconnect Programming

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IEEE TRANSACTIONS ON ADVANCED PACKAGING 2010年第2期33卷 362-369页

作者： Rabieirad, Laleh Martinez, Edgar J. Mohammadi, Saeed Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Purdue Univ Birck Nanotechnol Ctr W Lafayette IN 47907 USA Univ Illinois Coll Engn Urbana IL 61820 USA

A configurable integration technology suitable for implementing application specific radio-frequency (RF) and microwave circuits is presented. This postfabrication integration scheme is compatible with complementary metal-oxide-semiconductor (CMOS) technology and utilizes room temperature deposited Parylene-N as low loss and low permittivity dielectric material. Interconnect lines, inductors, and transmission lines fabricated on top of arrays of prefabricated 0.13 mu m and 90 nm CMOS transistors coated with Parylene-N are configured to design interconnect programmable RF and microwave circuits. The technology is used to demonstrate three proof of concept interconnect programmable narrowband amplifiers. These amplifiers have center frequencies of 5.5, 6.4, and 18 GHz with forward gain S-21 of 16.6, 11, and 18.7 dB, respectively. Fabrication simplicity and programmable nature of this technology compared to standard application specific integrated circuit (ASIC) fabrication lowers the cost and time to market of individual ASIC chip.

关键词： Coplanar waveguide (CPW) transmission line inductor interconnect low-k dielectric material narrowband amplifiers Parylene-N programmable circuits radio frequency (RF)

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Real-time Low-energy Fall Detection Algorithm with a programmable Truncated MAC

Real-time Low-energy Fall Detection Algorithm with a Program...

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32nd Annual International Conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBC 10)

作者： Solaz, Manuel de la Guia Bourke, Alan Conway, Richard Nelson, John OLaighin, Gearoid Univ Limerick Elect & Comp Engn Dept Limerick Ireland Natl Univ Ireland Galway Dept Elect Engn Galway Ireland

ISBN: (纸本)9781424441242

The ability to discriminate between falls and activities of daily living (ADL) has been investigated by using tri-axial accelerometer sensors, mounted on the trunk and using simulated falls performed by young healthy subjects under supervised conditions and ADL performed by elderly subjects. In this paper we propose a power-aware real-time fall detection integrated circuit (IC) that can distinguish Falls from ADL by processing the accelerations measured during 240 falls and 240 ADL. In the proposed fixed point custom DSP architecture, a threshold algorithm was implemented to analyze the effectiveness of programmable Truncated Multiplication regarding power reduction while maintaining a high output accuracy. The presented system runs a real time implementation of the algorithm on a low power architecture that allows up to 23% power savings through its digital blocks when compared to a standard implementation, without any accuracy loss.

关键词： DSP activities of daily living biomedical equipment biomedical measurement digital signal processing gait analysis measured acceleration processing medical signal processing monitoring applications patient monitoring power-aware real-time fall detection integrated circuit power-aware real-time low-energy fall detection algorithm programmable circuits real-time systems

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A CMOS programmable Gain Amplifier with a Novel DC-offset Cancellation Technique

A CMOS Programmable Gain Amplifier with a Novel DC-offset Ca...

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32nd Annual Custom Integrated circuits Conference CICC

作者： Chu, Xiaojie Lin, Min Gong, Zheng Shi, Yin Dai, Fa Foster Suzhou CAS Semicond Integrated Technol Res Ctr Suzhou 215021 Jiangsu Peoples R China Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

ISBN: (纸本)9781424457601

A programmable gain amplifier (PGA) with a novel DC offset cancellation (DCOC) technique for IEEE 802.11b/g wireless LAN direct-conversion receiver (DCR) is presented. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this PGA design. A gain tuning range of 0 dB to 56 dB with 2 dB per step is achieved. The DCOC loop is based on a voltage-current negative feedback that includes a switchable bandwidth algorithm to speed up the settling time of DCOC. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in a 0.13 mu m CMOS technology, this PGA dissipates 9.7 mW from a 1.2 V supply voltage and occupies an area of 0.17 mm(2).

关键词： CMOS integrated circuits CMOS programmable gain amplifier DC-DC power convertors DC-offset cancellation technique Miller compensation feedback gain 0 dB to 56 dB network analysis operational amplifier operational amplifiers power 9.7 mW programmable circuits size 0.13 mum voltage 1.2 V voltage-current negative feedback wireless LAN wireless LAN direct-conversion receiver

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Adaptive Packet Sizing for OTAP of PSoC Based Interface Board in WSN

Adaptive Packet Sizing for OTAP of PSoC Based Interface Boar...

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22nd International Conference on Microelectronics (ICM 2010)

作者： Adly, I. Ragai, H. F. Elhennawy, A. E. Shehata, K. A. Ain Shams Univ Fac Engn Dept Elect Engn Cairo Egypt French Univ Engn Coll Cairo Egypt Arab Acad Sci & Technol Engn Coll Cairo Egypt

ISBN: (纸本)9781612841519

Adaptive packet sizing techniques are widely used in wireless communication to enhance the link reliability. Typically, shorter packets are less error prone than longer packets. Adaptive packet size technique is used in IEEE 802.11 wireless network to enhance link reliability and packet delivery ratio. In this work, we adopt this technique to work in IEEE 802.15.4 based networks, and specifically in wireless sensor networks. A special protocol is designed to implement adaptive packet size transmission in WSN. In WSN, different mote designs and implementations are relying on the use of programmable circuits in their sensor interface boards. Delivering new firmware to these circuits by means of OTAP ( Over The Air Programming) requires a reliable link between base station and target mote. Such reliable link can be achieved using the proposed adaptive packet sizing protocol. A testbed based on such scenario is constructed and the proposed protocol was tested to send new firmware update data to the target mote in its distant location under different environmental conditions.

关键词： IEEE 802.11 wireless network IEEE 802.15.4 based networks OTAP PSoC based interface board WSN Zigbee adaptive packet sizing firmware firmware link reliability over the air programming packet delivery ratio programmable circuits programmable circuits proto

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A CMOS Imager With a programmable Bit-Serial Column-Parallel SIMD/MIMD Processor

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2009年第11期56卷 2534-2545页

作者： Yamashita, Hirofumi Sodini, Charles G. Toshiba Co Ltd Semicond Co Syst LSI Div Yokohama Kanagawa 2478585 Japan MIT Cambridge MA 02139 USA

An imager with an integrated fully programmable bit-serial column-parallel processor is proposed to meet the demand for a compact and versatile system-on-imager chip for consumer applications. The on-imager processor is targeting a computationally intensive low-level image processing task. The processor is physically arranged as a densely packed 2-D processing element (PE) array at an imager column level. The digital processor has a multiple-instruction-multiple-data (MIMD) architecture configuring multiple column-parallel single-instruction -multiple-data (SIMD) processors. The prototype imager chip with 128 x 128 pixels and 4 x 128 PE array designed with 0.6-mu m technology was fabricated, and its functionality was tested. The estimation of performance level of the proposed processor architecture with an advanced technology such as the 0.09-mu m process technology shows that the proposed imager chip architecture has a potential of giga sum operations per second per square millimeter class processing performance.

关键词： Array signal processing CMOS image sensors CMOS integrated circuits image processing intelligent sensors parallel processing programmable circuits

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A 750-MHz 6-b Adaptive Floating-Gate Quantizer in 0.35-μm CMOS

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2009年第7期56卷 1301-1312页

作者： Wong, Yanyi Liu Cohen, Marc H. Abshire, Pamela A. Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Univ Maryland Clark Sch Engn Syst Res Inst College Pk MD 20742 USA Prognosys Inc LLC Alexandria VA 22308 USA

A 6-b 750-MS/s flash analog-to-digital converter ( ADC) uses nonvolatile analog storage for reference levels and achieves a signal-to-noise-plus-distortion ratio (SNDR) and a spurious-free dynamic range of 37.2 and 48.6 dB, respectively. The architecture comprises an array of adaptive floating-gate comparators that enables storage and programming of reference levels, eliminating the need for resistive ladders. Reference levels may be programmed either manually by the user or autonomously during normal analog-to-digital conversion. Autonomous programming achieves histogram equalization by adjusting reference levels for finer resolution and greater sensitivity at frequently visited signal values. When programmed manually, the ADC achieves 34.3-dB SNDR at 750 MS/s for input frequencies up to 2.07X Nyquist rate, with a differential full-scale input range of 1 V. We observe integral nonlinearity and differential nonlinearity of less than 0.27 least significant bit at the Nyquist rate. One-month continuous operation shows no signs of reference-level drift due to charge leakage and maintains a constant bit error rate of 2.93 x 10(-9) sample.

关键词： Adaptive equalizers adaptive signal detection analog-to-digital conversion charge injection EPROM equalizers flash ADC floating gate histogram equalization learning systems mixed analog-to-digital integrated circuits nonlinear circuits nonvolatile analog storage Nyquist rate conversion programmable circuits quantization training tunable circuits and devices tunneling unsupervised learning

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Signal Conditioning Based On programmable Analog circuits

Signal Conditioning Based On Programmable Analog Circuits

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International Conference on Mixed Design of Integrated circuits and Systems (MIXDES)

作者： P. Pietrzak W. Tylman Z. Kulesza B. Pekoslawski M. Mularczyk A. Napieralski Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland

programmable circuits are commonly used class of electronic devices. In practice this term usually refers to microcontrollers with different kind of programmable memories and to programmable logic circuits (PAL, CPLD, FPGA). Most of these devices are digital circuits. Thanks to the huge progress in miniaturization of electronic circuits, the new class of devices -programmable analog circuits - was put on the market. These circuits bring new possibilities to design electronic circuit. One of the most promising fields of application is construction of analog signal conditioning circuits. This paper describes feature and parameters of sample programmable analog circuits. It depicts internal structure and theory of operation of these devices. One of commercially available programmable analog circuits was used in development of signal conditioning block for vibration measurement system. It works as programmable gain amplifier and low-pass anti-aliasing filter with programmable cut-off frequency. Amplifier transient characteristics for different gain values and frequency response of the filter were measured

关键词： Analog circuits Electronic circuits Filters programmable circuits Consumer electronics Microcontrollers Logic circuits Field programmable gate arrays Digital circuits Vibration measurement

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A DESIGN METHOD OF SWITCHED-CAPACITOR POWER CONVERTERS BY EMPLOYING A RING-TYPE POWER CONVERTER

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INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL 2009年第10A期5卷 2927-2938页

作者： Eguchi, Kei Oota, Ichirou Terada, Shinya Inoue, Takahiro Shizuoka Univ Dept Technol Educ Suruga Ku Shizuoka 4228529 Japan Kumamoto Natl Coll Technol Dept Informat & Commmun Kumamoto 8611102 Japan Kumamoto Univ Dept Elect & Comp Engn Kumamoto 8608555 Japan

To solve the flexibility problem in conversion modes, we propose a design method for switched-capacitor (SC) power converters by using a versatile SC converter, and derive theoretical formulas to give circuit properties such as output voltage, power efficiency, etc. According to conditions specified by a user, the proposed converter offers the circuit structure realizing a DC-DC/DC-AC/AC-DC/AC-AC mode of operation and circuit characteristics. Although most of conventional converters offer only one conversion mode, the proposed versatile converter employing, a ring-type power converter can achieve four conversion modes by controlling the timing of clock pulses. Moreover, the proposed analysis technique can provide theoretical results that am more accurate titan conventional techniques, because the influence of on-resistances is considered in the proposed technique, where circuit characteristics are analyzed by assuming an equivalent circuit of the converter block. The validity of circuit design. and theoretical results is confirmed by SPICE simulations. The simulation results show that the proposed system can offer the specified circuit structure and its characteristics.

关键词： Switched capacitor circuits programmable circuits Power converters Versatile converters Ring-type converters Coil-less circuits

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Caspar: Hardware patching for multicore processors 09

Caspar: Hardware patching for multicore processors

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ilya Wagner Valeria Bertacco University of Michigan Ann Arbor MI USA

ISBN: (纸本)9783981080155

Ensuring correctness of execution of complex multi-core processor systems deployed in the field remains to this day an extremely challenging task. The major part of this effort is concentrated on design verification, where different pre- and post-silicon techniques are used to guarantee that devices behave exactly as stated in the specification. Unfortunately, the performance of even state-of-the-art validation tools lags behind the growing complexity of multi-core designs. Therefore, subtle bugs still slip into released components, causing incorrect computational results, or even compromising the security of the end-user systems. In this work we present Caspar - an approach for in-the-field patching of the memory subsystem hardware in multi-core chips. Caspar relies on a checkpointing system, which periodically logs the state of the chip, and a novel error detection and recovery scheme, which uses a simplified mode of operation to bypass cache coherence and consistency errors. The implementation of Caspar employs hardware detectors: on-die programmable circuits to identify system's configurations that may lead to bugs, and to trigger recovery and bypass. Our experimental results show that Caspar can be used effectively to detect and bypass a variety of memory subsystem bugs, with as little as 2% performance impact and 6% area overhead during bug-free operation.

关键词： Hardware Multicore processing Computer bugs Coherence Detectors Checkpointing Runtime Protocols Security programmable circuits

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