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29th International Conference on Parallel and Distributed Computing (Euro-Par)

作者： Lordan, Francesc Puigdemunt, Gabriel Verges, Pere Conejero, Javier Ejarque, Jorge Badia, Rosa M. Barcelona Supercomp Ctr Barcelona Spain Univ Calif Irvine Irvine CA USA

ISBN: (纸本)9783031396977;9783031396984

The scale and heterogeneity of exascale systems increment the complexity of programming applications exploiting them. Task-based approaches with support for nested tasks are a good-fitting model for them because of the flexibility lying in the task concept. Resembling the hierarchical organization of the hardware, this paper proposes establishing a hierarchy in the application workflow for mapping coarse-grain tasks to the broader hardware components and finer-grain tasks to the lowest levels of the resource hierarchy to benefit from lower-latency and higher-bandwidth communications and exploiting locality. Building on a proposed mechanism to encapsulate within the task the management of its finer-grain parallelism, the paper presents a hierarchical peer-to-peer engine orchestrating the execution of workflow hierarchies with fully-decentralized management. The tests conducted on the MareNostrum 4 supercomputer using a prototype implementation prove the validity of the proposal supporting the execution of up to 707,653 tasks using 2,400 cores and achieving speedups of up to 106 times faster than executions of a single workflow and centralized management.

关键词： distributed systems exascale task-based programming model workflow hierarchy runtime system peer-to-peer decentralized management

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Design and Implementation of Data Flow programming Language DFC2 23

Design and Implementation of Data Flow Programming Language ...

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52nd International Conference on Parallel Processing (ICPP)

作者： Luo, Qiuming Liu, Senhong He, Weikai Du, Zheng Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Guangdong Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9798400708428

This article presents the design and development of a dataflow programming language called DFC2 (DataFlow C, version 2) based on the dataflow programming model. The DFC2 compiler is responsible for converting the DFC2 language into C++ language, which is then compiled into an executable file by the C++ compiler. DFC2 is designed to be user-friendly and easy to use by adhering to the traditional imperative programming language model. It also allows for the reuse of existing C language code to reduce development costs. DFC2 distinguishes between graph functions, which are automatically parallelized, and func functions, which are not, giving users greater control over the level of parallelism. Users can describe dataflow graphs at both the inter-function and intra-function levels. This article also implements an optimization framework for the DFC2 compiler and analyzes the optimization results. It demonstrates that with the introduction of conditional constant propagation and dead code elimination, it is possible to reduce execution time by up to 30% in the best-case scenario and an average of approximately 6%.

关键词： programming model Dataflow execution model Dataflow programming language DFC2 language

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Untangling Modern Parallel programming models 22

Untangling Modern Parallel Programming Models

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International Workshop on OpenCL

作者： Michael Kinsner Ben Ashbaugh James Brodman Greg Lueck John Pennycook Roland Schulz Intel Corporation Canada Intel Corporation United States

ISBN: (纸本)9781450396585

Modern hardware is increasingly rich in diversity, including CPUs, GPUs, FPGAs and more, with new and novel architectures constantly emerging. To provide differentiation between these devices, each is typically built around architectures optimized for some classes of application or some patterns of parallelism. Numerous computational cores, varying levels of hardware vectorization, and other degrees of architectural freedom exist across the many hardware options. The need to efficiently utilize diverse hardware has led to emergence of a wide variety of programming models, execution models, and languages, and has simultaneously led to a complex landscape of confused and often conflicting terminology and abstractions. This reality makes it challenging for developers to comprehend and then choose a programming model that fits with their applications and mental model, particularly when more than one target architecture or vendor is of interest. This talk strives to untangle the landscape of modern parallel programming models, to help developers understand how the models and options relate to each other, and to frame how to think about their specific algorithms when expressing them in code. Although experienced developers typically understand much of the terminology and the relationships between models, a holistic presentation of the material is of strong value, as evidenced by feedback from parallel programming experts that have seen previews of this presentation. To begin, a brief overview will be presented to frame parallel programming and offload compute programming models, followed by characterization of the Single Program Multiple Data (SPMD) abstract model and the power it exhibits when mapping to multiple classes of architecture. We will discuss how fundamental design decisions within a compiler impact the mapping from source code to an underlying programming model, highlighting that the same code can be lowered to multiple models. This is particularly relevant i

关键词： SIMD SPMD programming model OpenCL SYCL CUDA

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Experience Migrating OpenCL to SYCL: A Case Study on Searches for Potential Off-Target Sites of Cas9 RNA-Guided Endonucleases on AMD GPUs 36

Experience Migrating OpenCL to SYCL: A Case Study on Searche...

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36th IEEE International System-on-Chip Conference (SOCC)

作者： Jin, Zheming Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9798350300116

Cas-OFFinder is a popular application for genome editing. Its OpenCL implementation searches potential off-target sites in parallel on a GPU. In this work, we describe our experience migrating the application from OpenCL to SYCL. Evaluating the performance of the OpenCL and SYCL applications using human genome sequences shows that the SYCL program could achieve performance portability on the target GPUs. Exploring the optimizations of the hotspot kernel in SYCL may further improve the performance of the application by 9% to 23%.

关键词： programming model heterogeneous computing sequence analysis

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Understanding SYCL Portability for Pseudorandom Number Generation: a Case Study with Gene-Expression Connectivity Mapping

Understanding SYCL Portability for Pseudorandom Number Gener...

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37th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Jin, Zheming Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9798350311990

Towards the goal of improving functional and performance portability of SYCL, we study a bioinformatics application that has been accelerated with CUDA and fast pseudorandom number generation on a GPU. We describe the experience of migrating pseudorandom number generation from CUDA to SYCL, evaluate the performance of pseudorandom number generators using the CUDA random number generation library, suggest the support of the XORWOW pseudorandom number generator in the oneAPI math kernel library (oneMKL) interface for performance portability, and identify the performance gap using the MKL interface in SYCL that supports pseudorandom number generation with third-party libraries. We hope that the results are valuable for the development of the SYCL ecosystem.

关键词： Portability programming model Pseudorandom number generation Bioinformatics

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Logical Time for Reactive Software

Logical Time for Reactive Software

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Cyber-Physical Systems and Internet-of-Things Week (CPS-IoT Week)

作者： Lohstroh, Marten Lee, Edward A. Edwards, Stephen A. Broman, David Univ Calif Berkeley Berkeley CA 94720 USA Columbia Univ New York NY USA KTH Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9798400700491

Timing is an essential feature of reactive software. It is not just a performance metric, but rather forms a core part of the semantics of programs. This paper argues for a notion of logical time that serves as an engineering model to complement a notion of physical time, which models the physical passage of time. programming models that embrace logical time can provide deterministic concurrency, better analyzability, and practical realizations of timing-sensitive applications. We give definitions for physical and logical time and review some languages and formalisms that embrace logical time.

关键词： timing reactive systems programming model software

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Optimal land allocation to crop production in different decision priorities and water availability scenarios: East Azerbaijan province of Iran

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ARCHIVES OF AGRONOMY AND SOIL SCIENCE 2022年第5期68卷 597-614页

作者： Mohammadzadeh, Arash Vafabakhsh, Javad Mahdavi Damghani, Abdolmajid Deihimfard, Reza Shahid Beheshti Univ Environm Sci Res Inst Dept Agroecol Tehran Iran AREEO Khorasan Razavi Agr & Nat Resources Res & Educ Ct Seed & Plant Improvement Res Dept Mashhad Razavi Khorasan Iran

Optimal cropping pattern of Maragheh-Bonab plain was determined in different decision priorities (from viewpoint of farmers and experts) and annually water availability scenarios [60, 80 and 100 MCM (million cubic meters)/year]. Goal programming model was applied to the optimization of cropping pattern with considering eight goals. In the optimal cropping pattern from viewpoint of farmers, water consumption was reduced compared to existing condition about 42%, 32%, and 3% at 60, 80, and 100 MCM/year scenarios, respectively. While, from viewpoint of experts, this reduction was about 55%, 32%, and 32% for 60, 80, and 100 MCM/year scenarios, respectively. At 60 MCM/year scenario, total net return was calculated lower than the existing cropping pattern about 11% and 45% from the viewpoint of farmers and experts, respectively. However, optimization at 80 and 100 MCM/year scenarios, increased total net return compared to existing condition about 14% and 24% from the viewpoint of farmers and 14% and 14% from the viewpoint of experts, respectively. In the optimal cropping patterns, despite lower water consumption, the amount of net return, economic water productivity, economic energy, and land productivity increased against a decrease in employment, global warming potential, and environmental impacts of pesticides in the whole area.

关键词： Optimal cropping pattern programming model optimization environmental impacts

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Mint: An Accelerator For Mining Temporal Motifs 55

Mint: An Accelerator For Mining Temporal Motifs

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55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Talati, Nishil Ye, Haojie Vedula, Sanketh Chen, Kuan-Yu Chen, Yuhan Liu, Daniel Yuan, Yichao Blaauw, David Bronstein, Alex Mudge, Trevor Dreslinski, Ronald Univ Michigan Comp Sci & Engn Ann Arbor MI 48109 USA Technion Israel Inst Technol Comp Sci Dept Haifa Israel Univ Michigan Elect & Comp Engn Ann Arbor MI USA

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

A variety of complex systems, including social and communication networks, financial markets, biology, and neuroscience are modeled using temporal graphs that contain a set of nodes and directed timestamped edges. Temporal motifs in temporal graphs are generalized from subgraph patterns in static graphs in that they also account for edge ordering and time duration, in addition to the graph structure. Mining temporal motifs is a fundamental problem used in several application domains. However, existing software frameworks offer suboptimal performance due to high algorithmic complexity and irregular memory accesses of temporal motif mining. This paper presents Mint-a novel accelerator architecture and a programming model for mining temporal motifs efficiently. We first divide this workload into three fundamental tasks: search, book-keeping, and backtracking. Based on this, we propose a task-centric programming model that enables decoupled, asynchronous execution. This model unlocks massive opportunities for parallelism, and allows storing task context information on-chip. To best utilize the proposed programming model, we design a domain-specific hardware accelerator using its data path and memory subsystem design to cater to the unique workload characteristics of temporal motif mining. To further improve performance, we propose a novel optimization called search index memoization that significantly reduces memory traffic. We comprehensively compare the performance of Mint with state-of-the-art temporal motif mining software frameworks (both approximate and exact) running on both CPU and GPU, and show 9 x-2576 x benefit in performance.

关键词： hardware accelerator programming model temporal motif mining

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Linked Data Processing for Human-in-the-Loop in Cyber-Physical Systems

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IEEE TRANSACTIONS ON COMPUTATIONAL SOCIAL SYSTEMS 2021年第5期8卷 1238-1248页

作者： Zheng, Zhigao Mumtaz, Shahid Khosravi, Mohammad R. Menon, Varun G. Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan 430074 Peoples R China Univ Santiago Inst Telecomunicacoes P-3810193 Aveiro Portugal Persian Gulf Univ Dept Comp Engn Bushehr *** Iran Shiraz Univ Technol Telecommun Grp Shiraz *** Iran SCMS Sch Engn & Technol Dept Comp Sci & Engn Ernakulam 683576 India

There are several kinds of smart devices, such as smartphones, sensors, and smart wearable devices, included in the Human-in-the-Loop (HITL) system, but different devices have their own data processing and programming paradigm. Programmers usually need to design the same data processing logic for different devices by using a different programming model. How to mapping the same code to different devices without any change is an emerging topic in the HITL system. Furthermore, the intelligent data processing for the smart CPS sector is experiencing significant growth in data volume, driven by a large number of smart devices that are anticipated in the near further. All these smart devices are expected to improve the overall HITL system performance marvelously. A large number of devices can also outstandingly increase the data volume, which needs to be processed in real time. How to process large-scale data on a smart device in real time is another challenge. Focused on these challenges, this article proposed a computing device-aware HITL CPS data processing framework, named Barge, aiming to map the regular code to the different hardware without any change. In Barge, a semantic model, an architecture-driven programming model, and a graph partition scheme are included. The semantic model is used to express the user-defined graph algorithms by using the domain-specific language. The architecture-driven programming model will execute the graph algorithms on a different device in parallel. Furthermore, the graph partition scheme will partition the large-scale graphs into suitable partitions by aware of the topology to make the partitioned data suitable for kinds of smart devices. We believe that our work would open a wide range of opportunities to improve the performance of large-scale graph processing for HITL systems.

关键词： Data models Data processing programming Graphics processing units Computer architecture Computational modeling Smart devices Cyber-physical systems (CPSs) data partition graph computing Human-in-the-Loop (HITL) new architecture programming model semantic model

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Analysis of Validating and Verifying OpenACC Compilers 3.0 and Above 9

Analysis of Validating and Verifying OpenACC Compilers 3.0 a...

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9th Workshop on Accelerator programming Using Directives (WACCPD)

作者： Jarmusch, Aaron Liu, Aaron Munley, Christian Horta, Daniel Ravichandran, Vaidhyanathan Denny, Joel Friedline, Kyle Chandrasekaran, Sunita Univ Delaware Newark DE 19716 USA Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9781665490191

OpenACC is a high-level directive-based parallel programming model that can manage the sophistication of heterogeneity in architectures and abstract it from the users. The portability of the model across CPUs and accelerators has gained the model a wide variety of users. This means it is also crucial to analyze the reliability of the compilers' implementations. To address this challenge, the OpenACC Validation and Verification team has proposed a validation testsuite to verify the OpenACC implementations across various compilers with an infrastructure for a more streamlined execution. This paper will cover the following aspects: (a) the new developments since the last publication on the testsuite, (b) outline the use of the infrastructure, (c) discuss tests that highlight our workflow process, (d) analyze the results from executing the testsuite on various systems, and (e) outline future developments.

关键词： Performance programming model Testsuite Validation Conformance

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