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25th ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

作者： Shalf, John Lawrence Berkeley Natl Lab NERSC CTO Berkeley CA 94720 USA

ISBN: (纸本)9780769549569;9781467362184

Our underlying machine model has presumed modest growth in parallelism, adherence to Amdahl ratios for speeds-and-feeds, weak-scaling for parallelism, uniform distance between processing elements within a node and between nodes in a system, and conservation of the all-important FLOP in our algorithm and software design. However, the new reality is that parallelism (particularly on-chip) is growing exponentially, bandwidth and memory capacity are increasingly scarce and force us towards strong-scaling, distance as measured by power and performance is increasingly non-uniform at all levels of the machine, and flops are now heavily discounted to the point that wasting any other resource to save a few flops is a losing proposition. The enormous mismatch between our ability to express concepts of locality and implicit parallelism in existing programming models subjects our codes to huge inefficiencies and reduced portability. Future programming models need to be designed to accommodate the first derivative of these emerging hardware trends (exponential parallelism growth, non-uniformity, SIMD width growth, and bandwidth conservation). The talk will discuss the evolution of this mismatch between hardware and abstract machine models, and discuss a path to develop hardware constructs that enable more efficient implementation of core programming model semantics (example PGAS-on-chip, fast global reduction networks). We can also explore software constructs that better reflect the real costs and layout of an algorithm onto the underlying machine architecture (example hierarchical data layout directives and programmable iteration spaces).

关键词： HPC data energy efficiency exascale manycore programming models

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Heterogeneous Task Scheduling for Accelerated OpenMP

Heterogeneous Task Scheduling for Accelerated OpenMP

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26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Scogland, Thomas R. W. Rountree, Barry Feng, Wu-chun de Supinski, Bronis R. Virginia Tech Dept Comp Sci Blacksburg VA 24060 USA Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9780769546759

Heterogeneous systems with CPUs and computational accelerators such as GPUs, FPGAs or the upcoming Intel MIC are becoming mainstream. In these systems, peak performance includes the performance of not just the CPUs but also all available accelerators. In spite of this fact, the majority of programming models for heterogeneous computing focus on only one of these. With the development of Accelerated OpenMP for GPUs, both from PGI and Cray, we have a clear path to extend traditional OpenMP applications incrementally to use GPUs. The extensions are geared toward switching from CPU parallelism to GPU parallelism. However they do not preserve the former while adding the latter. Thus computational potential is wasted since either the CPU cores or the GPU cores are left idle. Our goal is to create a runtime system that can intelligently divide an accelerated OpenMP region across all available resources automatically. This paper presents our proof-of-concept runtime system for dynamic task scheduling across CPUs and GPUs. Further, we motivate the addition of this system into the proposed OpenMP for Accelerators standard. Finally, we show that this option can produce as much as a two-fold performance improvement over using either the CPU or GPU alone.

关键词： GPGPU OpenMP programming models

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Simulating the Spread of Infectious Disease over Large Realistic Social Networks using Charm plus

Simulating the Spread of Infectious Disease over Large Reali...

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26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Bisset, Keith R. Aji, Ashwin M. Bohm, Eric Kale, Laxmikant V. Kamal, Tariq Marathe, Madhav V. Yeom, Jae-Seung Virginia Tech Virginia Bioinformat Inst Blacksburg VA 24061 USA Aalto TKK FIN-00076 Espoo Finland

ISBN: (纸本)9780769546766

Preventing and controlling outbreaks of infectious diseases such as pandemic influenza is a top public health priority. EpiSimdemics is an implementation of a scalable parallel algorithm to simulate the spread of contagion, including disease, fear and information, in large (10(8) individuals), realistic social contact networks using individual-based models. It also has a rich language for describing public policy and agent behavior. We describe CharmSimdemics and evaluate its performance on national scale populations. Charm++ is a machine independent parallel programming system, providing high-level mechanisms and strategies to facilitate the task of developing highly complex parallel applications. Our design includes mapping of application entities to tasks, leveraging the efficient and scalable communication, synchronization and load balancing strategies of Charm++. Our experimental results on a 768 core system show that the Charm++ version achieves up to a 4-fold increase in performance when compared to the MPI version.

关键词： Computational Epidemiology Parallel Efficiency and Scalability Agent Based Simulation programming models Charm plus MPI

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Seamlessly Portable Applications: Managing the Diversity of Modern Heterogeneous Systems

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2012年第4期8卷 42-42页

作者： Kicherer, Mario Nowak, Fabian Buchty, Rainer Karl, Wolfgang Karlsruhe Inst Technol D-76049 Karlsruhe Germany

Nowadays, many possible configurations of heterogeneous systems exist, posing several new challenges to application development: different types of processing units usually require individual programming models with dedicated runtime systems and accompanying libraries. If these are absent on an end-user system, e.g. because the respective hardware is not present, an application linked against these will break. This handicaps portability of applications being developed on one system and executed on other, differently configured heterogeneous systems. Moreover, the individual profit of different processing units is normally not known in advance. In this work, we propose a technique to effectively decouple applications from their accelerator-specific parts, respectively code. These parts are only linked on demand and thereby an application can be made portable across systems with different accelerators. As there are usually multiple hardware-specific implementations for a certain task, e.g., a CPU and a GPU version, a method is required to determine which are usable at all and which one is most suitable for execution on the current system. With our approach, application and hardware programmers can express the requirements and the abilities of the application and the hardware-specific implementations in a simplified manner. During runtime, the requirements and abilities are compared with regard to the present hardware in order to determine the usable implementations of a task. If multiple implementations are usable, an online-learning history-based selector is employed to determine the most efficient one. We show that our approach chooses the fastest usable implementation dynamically on several systems while introducing only a negligible overhead itself. Applied to an MPI application, our mechanism enables exploitation of local accelerators on different heterogeneous hosts without preliminary knowledge or modification of the application.

关键词： Design Performance Heterogeneity programming models adaptive systems

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The Odd Couple: Hardware and Software

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IEEE MICRO 2012年第4期32卷 2-2页

作者： Altman, Erik R. IBM

This column discusses topics of interest to the microarchitecture community, judging by Micro conference paper session topics and IEEE Micro issue themes. It also previews the two Cool Chips articles in the issue and ... 详细信息

关键词： GPU Memory Microarchitecture Superscalar Caches Energy Power Parallelization Concurrency Multicore Reliability Security Debugging Simulation Test programming models Reconfigurability Virtualization Big Data Data Centers Robots Vision Image Recognition

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International Conference on Computational Science, ICCS 2012 A Theory of Data Movement in Parallel Computations

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Procedia Computer Science 2012年 9卷 236-245页

作者： Victor Eijkhout Texas Advanced Computing Center The University of Texas at Austin Austin TX 78758

We propose a set-theoretic model for parallelism. The model is based on separate distributions of data and work. The major theoretic result is that communication can then be derived by formal reasoning. While the model has an immediate interpretation in distributed memory parallelism, we show that it can also accomodate multicore shared memory programming, as well as clusters with accelerators. The model gives rise in a natural way to objects that resemble the VecScatter construct in the PETSc library, or active messages in such packages as Charm++. Thus we argue that the model offers the prospect of an abstract programming system that can be compiled down to proven high-performance constructs.

关键词： Parallel programming programming models

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A programming Model for Spatio-temporal Data Streaming Applications

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Procedia Computer Science 2012年 9卷 1139-1148页

作者： Shigeru Imai Carlos A. Varela Computer Science Department Rensselaer Polytechnic Institute 110 Eighth Street Troy NY 12180 USA

In this paper, we describe a programming model to enable reasoning about spatio-temporal data streams. A spatio-temporal data stream is one where each datum is related to a point in space and time. For example, sensors in a plane record airspeeds ( va ) during a given ﬂight. Similarly, GPS units record an airplane's ﬂight path over the ground including ground speeds ( vg ) at different locations. An aircraft's airspeed and ground speed are related by the following mathematical formula:, where v a and α a are the aircraft airspeed and heading, and v w and α w are the wind speed and direction. Wind speeds and directions are typically forecast in 3,000-foot height intervals over discretely located ﬁx points in 6-12 hour ranges. Modeling the relationship between these spatio-temporal data streams allows us to estimate with high probability the likelihood of sensor failures and consequent erroneous data. Tragic airplane accidents (such as Air France's Flight 447 on June 1st, 2009 killing all 216 passengers and 12 aircrew aboard) could have been avoided by giving pilots better information which can be derived from inferring stochastic knowledge about spatio-temporal data streams. This work is a ﬁrst step in this direction.

关键词： programming models spatio-temporal data data streaming

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Mission-oriented middleware for sensor-driven scientific systems

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JOURNAL OF INTERNET SERVICES AND APPLICATIONS 2012年第1期3卷 133-139页

作者： Dearle, Alan Dobson, Simon Univ St Andrews Sch Comp Sci St Andrews Fife Scotland

Coordinating the networks needed for modern scientific data collection and control presents a significant challenge: they are typically power- and resource-constrained, operating in noisy and hostile environments, and need to adapt their behaviour to match their operation to their sensed environment while maintaining the scientific integrity of their observations. In this paper, we explore several aspects of managing and coordinating sensor-driven systems. We draw some conclusions about how to design, structure, and implement programming and middleware abstractions for long-lived and adaptive sensor networks.

关键词： Sensor networks Middleware programming models

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Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2012年第1期11卷 14-14页

作者： Terechko, Andrei Hoogerbrugge, Jan Alkadi, Ghiath Guntur, Surendra Lahiri, Anirban Duranton, Marc Wust, Clemens Christie, Phillip Nackaerts, Axel Kumar, Aatish NXP Semicond NL-5656 AE Eindhoven Netherlands NXP Semicond Eindhoven Netherlands

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area-and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores;microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H. 264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm(2) and 8.6 mm(2), respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

关键词： Design Experimentation Performance Algorithms Languages Parallelism processor architecture multiprocessor heterogeneous accelerators embedded systems multimedia programming models design space exploration

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Algorithm level power efficiency optimization for CPU-GPU processing element in data intensive SIMD/SPMD computing

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2011年第2期71卷 245-253页

作者： Ren, Da Qi Univ Tokyo Dept Comp Sci Bunkyo Ku Tokyo 1130033 Japan CREST JST Tokyo Japan

Power efficiency investigation has been required in each level of a High Performance Computing (HPC) system because of the increasing computation demands of scientific and engineering applications. Focusing on handling the critical design constraints in the software level that run beyond a parallel system composed of huge numbers of power-hungry components, we optimize HPC program design in order to achieve the best possible power performance on the target hardware platform. The power performance of a CUDA Processing Element (PE) is determined by both hardware factors including power features of each component including with CPU, GPU, main memory and PCI buses, and their interconnection architecture;and software factors including algorithm design and the character of executable instructions performed on it. In this paper, approaches to model and evaluate the power consumption of large scale SIMD computation by CUDA PEs on multi-core and GPU platforms are introduced. The model allows obtaining design characteristic values at the early programming stage, thus benefitting programmers by providing the necessary environment information for choosing the best power-efficient alternative. Based on the model, CPU Dynamic frequency scaling (DFS) can be applied on CUDA PE architecture that adjusts CPU frequency to enhance power efficiency of the entire PE without compromising its computing performance. The power model and power efficiency improvements of the new designs have been validated by measuring the new programs on the real GPU multiprocessing system. (C) 2010 Elsevier Inc. All rights reserved.

关键词： programming models Abstractions for data intensive computing Stream computing Green (power efficient) data intensive computing

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