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programming MULTIPROCESSORS WITH EXPLICITLY MANAGED MEMORY HIERARCHIES

COMPUTER 2009年第12期42卷 28-34页

作者： Schneider, Scott Yeom, Jae-Seung Nikolopoulos, Dimitrios S. Virginia Tech Dept Comp Sci Blacksburg VA 24061 USA Univ Crete Iraklion Greece

A study of two applications programmed using three models of varying complexity reveals that implicit management of locality can produce code with performance comparable to code generated from explicit management of l... 详细信息

关键词： programming Microprocessors Computational modeling Magnetic cores Arrays Data mining Multicore processors Hardware Cell Broadband Engine processor Explicitly managed memory hierarchies programming models

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An Extension of the StarSs programming Model for Platforms with Multiple GPUs

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15th International Euro-Par Conference on Parallel Computing

作者： Ayguade, Eduard Badia, Rosa M. Igual, Francisco D. Labarta, Jesus Mayo, Rafael Quintana-Orti, Enrique S. CNS BSC Nexus 2 BldgC Jordi Girona 29 Barcelona 08034 Spain CSIC Madrid Spain Univ Jaume 1 Dept Ingn Ciensia Comp Castellon de La Plana 12 Spain

ISBN: (纸本)9783642038686

While general-purpose homogeneous multi-core architectures are becoming ubiquitous, there are clear indications that, for a number of important applications, a better performance/power ratio can be attained using specialized hardware accelerators. These accelerators require specific SDK or programming languages which are not always easy to program. Thus, the impact of the new programming paradigms on the programmer's productivity will determine their success in the high-performance computing arena. In this paper we present CPU Superscalar (GPUSs), an extension of the Star Superscalar programming model that targets the parallelization of applications on platforms consisting of a general-purpose processor connected with multiple graphics processors. GPUSs deals with architecture heterogeneity and separate memory address spaces;while preserving simplicity and portability. Preliminary experimental results for a well-known operation in numerical linear algebra illustrate the correct;adaptation of the runtime to a multi-GPU system, attaining notable performance results.

关键词： Task-level parallelism graphics processors heterogeneous systems programming models

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Gears4Net-an Asynchronous programming Model

Gears4Net-an Asynchronous Programming Model

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38th International Conference on Parallel Processing

作者： Saternus, Martin Weis, Torben Holzapfel, Sebastian Wacker, Arno Univ Duisburg Essen Distributed Syst Grp D-47057 Duisburg Germany

ISBN: (纸本)9781424449231

We propose a programming model for scalable distributed applications. Our programming model aims at applications which have to handle a high number of concurrent network connections in parallel. Such load characteristics appear in Web 2.0 applications and in scientific network simulators. The problem originates at the I/O API provided by the operating system. Blocking I/O is easy to use, but in large scale scenarios the usage of threads and memory is excessive. Non-blocking I/O can theoretically reduce the resource consumption, but it is awkward to program. Our approach utilizes a special language feature found in Microsoft's C# and Python and combines the best of both worlds. programming is almost as easy as with blocking I/O and the resource usage is nearly optimal. Our solution is implemented on top of Microsoft .NET or Mono/Linux respectively and does not require any changes to the operating system, which is very valuable for its practical application.

关键词： Parallel programming programming models Concurrency

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Adaptivity in Risk and Emergency Management Applications on Pervasive Grids

Adaptivity in Risk and Emergency Management Applications on ...

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10th International Symposium on Pervasive Systems, Algorithms, and Networks

作者： Bertolli, Carlo Mencagli, Gabriele Vanneschi, Marco Univ Pisa Dept Comp Sci Largo Bruno Pontecorvo 3 I-56125 Pisa Italy

ISBN: (纸本)9781424454037

Pervasive Grid computing platforms are composed of a variety of xed and mobile nodes, interconnected through multiple wireless and wired network technologies. Pervasive Grid Applications must adapt themselves to the state of their surrounding environment which includes environmental data (e.g. collected from sensors) and the state of the used resources (e.g. network or node states). Adaptation is especially important if we consider complex High-Performance Pervasive Grid applications, such as intelligent transportation and emergency management. In this paper we investigate how to de ne adaptivity for complex Pervasive Grid applications by providing multiple versions of application parallel modules. The versions are de ned by exploiting different sequential algorithms and parallelization techniques. We introduce performance analysis tools for versions, which allow us to de ne specific selection policies of the best version to be executed, depending on the context. We show how each version is best suited to be executed on two application scenarios, also by means of experiments. To synthesize the contributions of this paper we introduce the ASSISTANT programming model, for adaptive Pervasive Grid applications.

关键词： Pervasive Grid High-Performance Risk and Emergency Management Adaptivity programming models

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A Frontier Approach to Testing the Averch-Johnson Hypothesis

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INTERNATIONAL JOURNAL OF THE ECONOMICS OF BUSINESS 2009年第3期16卷 347-363页

作者： Vitaliano, Donald F. Stella, Gregory P. Rensselaer Polytech Inst Dept Econ Troy NY 12180 USA New York State Dept Publ Serv Albany NY 12223 USA

The mathematical programming technique Data Envelopment Analysis is used to test the famous hypothesis of Averch and Johnson that utility regulation leads to overuse of capital because the regulated firm earns a return s greater than its cost of capital r, an implicit capital subsidy resulting in allocative inefficiency. Technical and allocative inefficiency are based on cost and production frontiers from 337 electric generating plants using 1970 data, and r is based on the Capital Asset Pricing Model. Significant capital overuse and general failure to minimize costs is detected, but a second-step regression analysis finds no relationship between the overuse and the s-r subsidy. A small updated data set covering the period 1980-2004 suggests that overuse of capital is no longer a problem, a result that may be owing to recent deregulation and restructuring.

关键词： Electric Utilities Economics of Regulation programming models

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On the Exploitation of Loop-level Parallelism in Embedded Applications

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2009年第2期8卷 10:1-10:34页

作者： Kejariwal, Arun Veidenbaum, Alexander V. Nicolau, Alexandru Girkar, Milind Tian, Xinmin Saito, Hideki Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA Intel Corp Intel Compiler Lab Santa Clara CA 95051 USA

Advances in the silicon technology have enabled increasing support for hardware parallelism in embedded processors. Vector units, multiple processors/cores, multithreading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. To what extent the available hardware parallelism can be exploited is directly dependent on the amount of parallelism inherent in the given application and the congruence between the granularity of hardware and application parallelism. This paper discusses how loop-level parallelism in embedded applications can be exploited in hardware and software. Specifically, it evaluates the efficacy of automatic loop parallelization and the performance potential of different types of parallelism, viz., true thread-level parallelism (TLP), speculative thread-level parallelism and vector parallelism, when executing loops. Additionally, it discusses the interaction between parallelization and vectorization. Applications from both the industry-standard EEMBC (R)(1) 1.1, EEMBC 2.0 and the academic MiBench embedded benchmark suites are analyzed using the Intel (R)(2) C compiler. The results show the performance that can be achieved today on real hardware and using a production compiler, provide upper bounds on the performance potential of the different types of thread-level parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.

关键词： Performance Measurement Multi-cores system-on-chip (Soc) programming models libraries multithreading vectorization thread-level speculation parallel loops

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A european perspective on supercomputing 09

A european perspective on supercomputing

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Proceedings of the 23rd international conference on Supercomputing

作者： Mateo Valero Barcelona Supercomputing Center - Centro Nacional de Supercomputación Barcelona Spain

ISBN: (纸本)9781605584980

Massive computing systems will be needed to maintain competitiveness in all areas of science, engineering and business, to provide both management efficiency and computing capability. From a systems management perspective, massive installations offer an efficient platform for resource sharing and service-oriented cloud computing; from a capability perspective, they allow unprecedented performance for supercomputing applications. With top supercomputing systems reaching the PetaFlop barrier, the next challenge is to devise technology to reach, and applications to take advantage of, ExaFlop performance. Multicore chips are already here but will grow in the next decade to several hundred cores. Although these chips will be used for general-purpose computing, they will be the tera-device components of future exascale *** is aware of the importance of having a well-structured supercomputing infrastructure, as well as the need to exchange experiences and know-how across the Union. Infrastructure projects such as the current DEISA (Distributed European Infrastructure for Supercomputing Applications) or the future PRACE (Partnership for Advanced Computing in Europe) aim at setting up such coordinated resources. PRACE, in particular, will create a world-class pan-European high performance computing service and infrastructure, managed as a single European entity. The service will include five superior supercomputing centers, strengthened by regional and national centers, working in collaboration through grid technologies. The BSC-CNS is the Spanish representative, one of five principal partners in the project (the others being Germany, France, UK and the Netherlands). The principal partner countries have agreed to contribute more to the PRACE budget, and to host the tier-0 machines which will form part of the distributed *** hit the power wall, the computing market is now undergoing a shaky era of dispersion, where many kinds of multicore alternat

关键词： programming models supercomputing infrastructure exascale computing supercomputing grids exaflop multicore architectures

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Achieving programming model abstractions for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2008年第1期16卷 34-44页

作者： Andrews, David Sass, Ron Anderson, Erik Agron, Jason Peck, Wesley Stevens, Jim Baijot, Fabrice Komp, Ed Univ Kansas Dept Elect Engn & Comp Sci Lawrence KS 66045 USA Univ N Carolina Dept Elect & Comp Engn Charlotte NC 28223 USA Univ So Calif Inst Informat Sci Los Angeles CA USA Univ Kansas Informat & Telecommun Technol Ctr Lawrence KS 66045 USA

This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.

关键词： field-programmable gate arrays (FPGAs) operating systems programming models reconfigurable computing

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Parallel programming of multi-processor SoC:: A HW-SW interface perspective

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INTERNATIONAL JOURNAL OF PARALLEL programming 2008年第1期36卷 68-92页

作者： Kriaa, Lobna Bouchhima, Aimen Gligor, Marius Fouillart, Anne-Marie Petrot, Frederic Jerraya, Ahmed-Amine TIMA Lab SLS Grp F-38031 Grenoble France Land & Joint Syst EDS DHD THALES F-92704 Colombes France

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.

关键词： programming models HW/SW interfaces heterogeneous MPSoC

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Convenience over correctness

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IEEE INTERNET COMPUTING 2008年第4期12卷 89-92页

作者： Vinoski, Steve Verivue

For decades, the RPC abstraction has been known to be fraught with serious problems related to partial failure, latency, and concurrency. Still, many developers continue to use RPC—some are even developing... 详细信息

关键词： Erlang REST RPC asynchronous messaging concurrency distributed systems latency partial failure programming languages programming models remote procedure call toward integration Computer programming Languages Concurrency partial failure Erlang Latency Distributed Systems

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