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30th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Malik, Gurshaant Lang, Ian Elmor Pellizoni, Rodolfo Kapre, Nachiket Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9781728199023

We can overcome the pessimism in worst-case routing latency analysis of timing-predictable Network-on-Chip (NoC) workloads by single digit factors through the use of a hybrid FPGA-optimized NoC. Timing-predictable FPGA-optimized NoCs such as HopliteBuf integrate stall-free FIFOs that are sized using offline, static analysis of a user-supplied flow pattern and rates. For certain bursty traffic and flow configurations, the static analysis delivers very large, sometimes infeasible, FIFO size bounds and large worst-case latency bounds. Alternatively, backpressure-based NoCs such as HopliteBP can operate with lower latencies for certain bursty flows. However, they suffer from severe pessimism in the analysis due to the effect of pipelining of packets and interleaving of flows at switch ports. As we show in this paper, a hybrid FPGA NoC that seamlessly composes both design styles on a per-switch basis, delivers the best of both worlds with improved feasibility (bounded operation), and tighter latency bounds. We select the NoC switch configuration though a novel evolutionary algorithm based on Maximum Likelihood Estimation (MLE). For synthetic (RANDOM, LOCAL) and real world (SpMV, Graph) workloads, we demonstrate approximate to 2-3x improvements in feasibility, approximate to 1-6.8x in worst-case latency while only requiring LUT cost approximate to 1-1.5x larger than the cheapest HopliteBuf solution. We also deploy and verify our NoC (PL) and MLE framework (PS) on a Pynq-Z1 to adapt and reconfigure NoC switches dynamically.

关键词： Architectures and Technology Methods and Tools programming models

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A Cyber Sensor Model for Cyber-Physical-Social Systems

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INTERNATIONAL JOURNAL OF AGRICULTURAL AND ENVIRONMENTAL INFORMATION SYSTEMS 2021年第1期12卷 80-94页

作者： Murdoch, Olga O'Grady, Michael J. O'Hare, Gregory M. P. Univ Coll Dublin Dublin Ireland Univ Coll Dublin Sch Comp Sci & Informat Dublin Ireland

Engineering sustainable cyber-physical-social systems demand a transdisciplinary approach. Within an arbitrary domain, many systems, including those of the physical and cyber categories, may already be in-situ;however, heterogeneity permeates such systems, for example, differing protocols, data formats, among others. Heterogeneity is not a deliberate feature of an arbitrary system;rather, it is the cumulative result of pragmatic decisions that were made during design and is driven by many different factors, some of which may not be technological. Nonetheless, heterogeneity represents a critical obstacle for system designers as they seek to harness and integrate diverse system elements to deliver innovative services. This obstacle is acutely manifested in cyber-physical-social systems when collecting and fusing data for evidence-based decision-making;social and human-derived data exacerbate the problem. This paper proposes a programming model for fusing information sources in cyber-physical-social systems. The efficacy of the model is validated via a usability analysis.

关键词： Applied Software Engineering Cyber-Physical-Social Computing Human Factors programming models

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Using a Shared SGX Enclave in the UNIX PAM Authentication Service 14

Using a Shared SGX Enclave in the UNIX PAM Authentication Se...

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14th Annual IEEE International Systems Conference (SysCon)

作者： Will, Newton C. Maziero, Carlos A. Univ Fed Parana Comp Sci Dept BR-81530015 Curitiba Parana Brazil

ISBN: (纸本)9781728153650

Confidentiality in the storage and handling of sensitive data is a central concern in computing security;one of the most sensitive data in computer systems is users' credentials. To ensure the confidentiality and integrity of sensitive data, developers can use a Trusted Execution Environment (TEE). One of such TEE is Intel Software Guard Extensions (SGX), which reduces the trusted computing base to a hardware/software concept called enclave. However, using SGX enclaves usually incurs in a performance impact in the application execution. In this paper we propose an enclave sharing approach to reduce the performance overhead in scenarios where multiple enclaves handle the same data. To evaluate this approach, we implemented a SGX-secured OS authentication service. Three prototypes were built, considering distinct concerns about security and performance. Results show that this approach can be used in high demand environments, presenting a small overhead.

关键词： Trusted execution programming models software architecture design patterns performance

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Tracking Performance Portability on the Yellow Brick Road to Exascale

Tracking Performance Portability on the Yellow Brick Road to...

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IEEE/ACM International Workshop on Performance, Portability and Productivity in HPC (P3HPC)

作者： Deakin, Tom Poenaru, Andrei Lin, Tom McIntosh-Smith, Simon Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9781665422871

With Exascale machines on our immediate horizon, there is a pressing need for applications to be made ready to best exploit these systems. However, there will be multiple paths to Exascale, with each system relying on processor and accelerator technologies from different vendors. As such, applications will be required to be portable between these different architectures, but it is also critical that they are efficient too. These double requirements for portability and efficiency begets the need for performance portability. In this study we survey the performance portability of different programming models, including the open standards OpenMP and SYCL, across the diverse landscape of Exascale and pre-Exascale processors from Intel, AMD, NVIDIA, Fujitsu, Marvell, and Amazon, together encompassing GPUs and CPUs based on both x86 and Arm architectures. We also take a historical view and analyse how performance portability has changed over the last year.

关键词： performance portability programming models

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Improving programming Support for Hardware Accelerators Through Automata Processing Abstractions

Improving Programming Support for Hardware Accelerators Thro...

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作者： Angstadt, Kevin University of Michigan

The adoption of hardware accelerators, such as Field-Programmable Gate Arrays, into general-purpose computation pipelines continues to rise, driven by recent trends in data collection and analysis as well as pressure from challenging physical design constraints in hardware. The architectural designs of many of these accelerators stand in stark contrast to the traditional von Neumann model of CPUs. Consequently, existing programming languages, maintenance tools, and techniques are not directly applicable to these devices, meaning that additional architectural knowledge is required for effective programming and configuration. Current programming models and techniques are akin to assembly-level programming on a CPU, thus placing significant burden on developers tasked with using these architectures. Because programming is currently performed at such low levels of abstraction, the software development process is tedious and challenging and hinders the adoption of hardware accelerators. This dissertation explores the thesis that theoretical finite automata provide a suitable abstraction for bridging the gap between high-level programming models and maintenance tools familiar to developers and the low-level hardware representations that enable high-performance execution on hardware accelerators. We adopt a principled hardware/software co-design methodology to develop a programming model providing the key properties that we observe are necessary for success, namely performance and scalability, ease of use, expressive power, and legacy support. First, we develop a framework that allows developers to port existing, legacy code to run on hardware accelerators by leveraging automata learning algorithms in a novel composition with software verification, string solvers, and high-performance automata architectures. Next, we design a domain-specific programming language to aid programmers writing pattern-searching algorithms and develop compilation algorithms to produce fi

关键词： automata programming models hardware accelerators hardware/software co-design Thesis

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The allscale framework architecture

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PARALLEL COMPUTING 2020年 99卷 102648-102648页

作者： Jordan, Herbert Gschwandtner, Philipp Thoman, Peter Zangerl, Peter Hirsch, Alexander Fahringer, Thomas Heller, Thomas Fey, Dietmar Univ Innsbruck Tech Str 21a A-6020 Innsbruck Austria Univ Erlangen Nurnberg Schlosspl 4 D-91058 Erlangen Germany

The tremendous challenge of developing applications efficiently utilizing the hardware provided by contemporary parallel systems of all scales is among the most limiting factors for the continuous growth of high performance computing. In this article, we present a novel architecture taking on this challenge by providing an infrastructure for the effective development of such applications. Our design combines the expressive power of modern C++, advanced compiler technology, and sophisticated runtime system solutions, with the goal of providing a clean separation of domain specific algorithms, resource management activities, and low-level hardware interactions - all required to be accounted for by high performance applications. The article covers the architecture design, its key aspects, and a first evaluation of the achievable performance of an application implemented based on the proposed infrastructure. (C) 2020 Published by Elsevier B.V.

关键词： programming models Parallel runtimes Runtimes High performance computing Extreme scale Parallel computing Space weather simulation Efficient computing Development efficiency Productivity

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Multi-tenant Pub/Sub Processing for Real-Time Data Streams 24th

Multi-tenant Pub/Sub Processing for Real-Time Data Streams

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International European Conference on Parallel and Distributed Computing (Euro-Par)

作者： Villalba, Alvaro Carrera, David Tech Univ Catalonia UPC Barcelona Spain Barcelona Supercomp Ctr BSC Barcelona Spain

ISBN: (纸本)9783030105495;9783030105488

Devices and sensors generate streams of data across a diversity of locations and protocols. That data usually reaches a central platform that is used to store and process the streams. Processing can be done in real time, with transformations and enrichment happening on-the-fly, but it can also happen after data is stored and organized in repositories. In the former case, stream processing technologies are required to operate on the data;in the latter batch analytics and queries are of common use. This paper introduces a runtime to dynamically construct data stream processing topologies based on user-supplied code. These dynamic topologies are built on-the-fly using a data subscription model defined by the applications that consume data. Each user-defined processing unit is called a Service Object. Every Service Object consumes input data streams and may produce output streams that others can consume. The subscription-based programing model enables multiple users to deploy their own data-processing services. The runtime does the dynamic forwarding of data and execution of Service Objects from different users. Data streams can originate in real-world devices or they can be the outputs of Service Objects. The runtime leverages Apache STORM for parallel data processing, that combined with dynamic user-code injection provides multi-tenant stream processing topologies. In this work we describe the runtime, its features and implementation details, as well as we include a performance evaluation of some of its core components.

关键词： Big Data Analytics Stream processing Real-time data processing programming models Internet of Things IoT

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Compiler Optimizations for Parallel Programs 1

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31st International Workshop on Languages and Compilers for Parallel Computing (LCPC)

作者： Doerfert, Johannes Finkel, Hal Argonne Natl Lab Argonne Leadership Comp Facil 9700 S Cass Ave Argonne IL 60439 USA

ISBN: (数字)9783030346270

ISBN: (纸本)9783030346270;9783030346263

This paper outlines a research and development program to enhance modern compiler technology, and the LLVM compiler infrastructure specifically, to directly optimize parallel-programming-model constructs. The goal is to produce higher-quality code, and moreover, to remove abstraction penalties generally associated with such constructs. We believe that such abstraction penalties are increasing in importance due to C++ parallel-algorithms libraries and other performance-portability-motivated programming methods. In addition, we will discuss when, and more importantly when not, explicit parallelism-awareness is necessary within the compiler in order to enable the desired optimization capabilities.

关键词： Parallel programming LLVM OpenMP Compiler optimizations Intermediate representation programming models

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Performance Portability across Diverse Computer Architectures

Performance Portability across Diverse Computer Architecture...

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IEEE/ACM International Workshop on Performance, Portability and Productivity in HPC (P3HPC)

作者： Deakin, Tom McIntosh-Smith, Simon Price, James Poenaru, Andrei Atkinson, Patrick Popa, Codrin Salmon, Justin Univ Bristol High Performance Comp Res Grp Bristol Avon England

ISBN: (纸本)9781728160030

Previous studies into performance portability have typically analysed a single application (and its various implementations) in isolation. In this study we explore the wider landscape of performance portability by considering a number of applications from across the space of dwarfs, written in multiple parallel programming models, and across a diverse set of architectures. We apply rigorous performance portability metrics, as defined by Pennycook et al [1]. We believe this is the broadest and most rigorous performance portability study to date, representing a far reaching exploration of the state of performance portability that is achievable today. We will present a summary of the performance portability of each application and programming model across our diverge range of twelve computer architectures, including six different server CPUs from five different vendors, five different GPUs from two different vendors, and one vector architecture. We will conclude with an analysis of the performance portability of key programming models in general, across different application spaces as well across differing architectures, allowing us to comment on more general performance portability principles.

关键词： performance portability productivity mini-app programming models

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A comparative study of GPU programming models and architectures using neural networks

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JOURNAL OF SUPERCOMPUTING 2012年第3期61卷 673-718页

作者： Pallipuram, Vivek K. Bhuiyan, Mohammad Smith, Melissa C. Clemson Univ Dept Elect & Comp Engn Clemson SC 29634 USA

Recently, General Purpose Graphical Processing Units (GP-GPUs) have been identified as an intriguing technology to accelerate numerous data-parallel algorithms. Several GPU architectures and programming models are beginning to emerge and establish their niche in the High-Performance Computing (HPC) community. New massively parallel architectures such as the Nvidia's Fermi and AMD/ATi's Radeon pack tremendous computing power in their large number of multiprocessors. Their performance is unleashed using one of the two GP-GPU programming models: Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL). Both of them offer constructs and features that have direct bearing on the application runtime performance. In this paper, we compare the two GP-GPU architectures and the two programming models using a two-level character recognition network. The two-level network is developed using four different Spiking Neural Network (SNN) models, each with different ratios of computation-to-communication requirements. To compare the architectures, we have chosen the two extremes of the SNN models for implementation of the aforementioned two-level network. An architectural performance comparison of the SNN application running on Nvidia's Fermi and AMD/ATi's Radeon is done using the OpenCL programming model exhausting all of the optimization strategies plausible for the two architectures. To compare the programming models, we implement the two-level network on Nvidia's Tesla C2050 based on the Fermi architecture. We present a hierarchy of implementations, where we successively add optimization techniques associated with the two programming models. We then compare the two programming models at these different levels of implementation and also present the effect of the network size (problem size) on the performance. We report significant application speed-up, as high as 1095x for the most computation intensive SNN neuron model, against a serial implementation on th

关键词： CUDA OpenCL Fermi Radeon Spiking neural network programming models Architectures Speed-up Profiler counters

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