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Towards high-performance packet processing on commodity multi-cores: current issues and future directions

Science China(Information Sciences) 2015年第12期58卷 28-43页

作者： TANG Lu YAN JinLi SUN ZhiGang LI Tao ZHANG MinXuan School of Computer National University of Defense Technology

The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing ***, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.

关键词： network commodity multi-core packet processing SKB DPDK

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A Reconfigurable Hardware Architecture for packet processing

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Chinese Journal of Electronics 2018年第2期27卷 428-432页

作者： DUAN Tong LAN Julong HU Yuxiang LIU Shiran National Digital Switching System & Engineering Technological Research Center

In this paper, we propose a reconfigurable packet processing hardware architecture for future switch,in which several protocol-independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture,any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost,the processor cost model and optimization algorithm are proposed. The Net FPGA-based implementation shows a throughput of 94 Gb/s with 64-B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.

关键词： packet processing Hardware architecture Reconfigurable Protocol-independent

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OpenTag: Tag-Based User-Driven In-Network packet processing on Commercial Network Devices

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IEICE TRANSACTIONS ON COMMUNICATIONS 2013年第1期E96B卷 31-39页

作者： Furuhashi, Ryoji Nakao, Akihiro Univ Tokyo Interfac Initiat Informat Studies Tokyo 1538904 Japan

Network slicing for wide-area coordinated packet processing has attracted attentions for improving efficiency of handling network traffic. We have recently proposed a tag-based network slicing mechanism called OpenTag, and introduced the prototype implementation of the OpenTag redirector on an evaluation board. In this paper, we investigate the integration, of the OpenTag redirector into a commercial network device. Our contributions are three-fold: (1) designing the architecture aiming OpenTag-capable intermediaries embedded on commercial network devices, (2) implementing a prototype of the embedded OpenTag redirector using the Advanced Mezzanine Card (AMC) which has an OCTEON network processor, (3) showing our implementation can tolerate high bandwidth environment.

关键词： network virtualization cloud computing network resource slicing packet processing disaster recovery

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Towards 100G packet processing: Challenges and Technologies

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BELL LABS TECHNICAL JOURNAL 2009年第2期14卷 57-79页

作者： Hermsmeyer, Christian Song, Haoyu Schlenk, Ralph Gemelli, Riccardo Bunse, Stephan Philips Kommun Ind AG Hardware Dev Private ISDN Nurnberg Germany Philips Kommun Ind AG Hardware Dev Private ISDN Glasgow Lanark Scotland Italtel Milan Italy Alcatel Lucent Bell Labs Packet Transport Networking Technol Dept Stuttgart Germany

Driven by media-rich and bandwidth-intensive Internet applications, 100 Gigabit Ethernet embodies the next logical and necessary line speed following 10G/40G, although enormous challenges exist. Can today's device technologies scale, or will new, disruptive approaches be required to overcome throughput and power density limitations? The evolution of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technology was analyzed concerning speed, density, power, and pin interfacing. While clock frequencies cannot keep up with the higher interface speeds, massive parallelism and deep pipelining are needed to scale the throughput. The state-of-the-art architectures and algorithms for every aspect of packet processing are described. In addition, we look at alternative memory concepts and cover some emerging technologies: asynchronous FPGAs as a means for boosting the system clock and serial interfaces reducing the pin count between devices. Thereby, economic considerations limit the choice between the options. We conclude that although significant effort is necessary in terms of device and board technology, economic 100G networking is viable. (C) 2009 Alcatel-Lucent.

关键词： serial I/O packet processing Field programmable gate arrays Throughput system clock

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packetUsher: Exploiting DPDK to accelerate compute-intensive packet processing

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COMPUTER COMMUNICATIONS 2020年 161卷 324-333页

作者： Ren, Qingqing Zhou, Liang Xu, Zhijun Zhang, Yujun Zhang, Lei Chinese Acad Sci Inst Comp Technol Beijing Peoples R China Univ Calif Riverside Riverside CA 92521 USA Hebei Univ Technol Tianjin Peoples R China

Many compute-intensive network applications such as application-layer traffic generator, Deep packet Inspection(DPI) and web servers are widely deployed on commodity PC for the reason of flexibility and cheap price. However, how to improve their performance on general purpose OS is challenging due to the high packet I/O related overheads. This paper presents packetUsher, a high-performance packets processing framework to remove these performance bottlenecks. In building packetUsher, we constructed a DPDK wrapper as the underlying packet I/O engine to accelerate packet transmission, and utilized the strategies of zero copy, batch processing and parallelism to improve packet processing. Through RFC2544 benchmark, we demonstrate that DPDK wrapper has excellent packets transmission capability. As a case study of packetUsher, we design and implement a commercial application-layer traffic generator. The experiment results show that the FPS (Flow Per Second) value of our traffic generator over packetUsher is more than 4 times of that over standard Linux platform. By comparison, the FPS value over packetUsher is about 3 times of that over existing methods (Netmap and PF_RING).

关键词： packet processing DPDK Performance improvement Commodity PC Traffic generation

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Using packet processing Object Modules Interchangeably as Stand-Alone Programs or "Multi-app" Components

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2016年第1期44卷 26-45页

作者： Duncan, Ralph Jungck, Peder Ross, Kenneth Mulcahy, Dwight Minh Nguyen CloudShield Technol Sunnyvale CA 94089 USA BAE Syst Intelligence & Secur Mclean VA USA Shape Secur Mountain View CA USA

The basic model for processing packets and routing them from one hardware system to another can be extended to describe virtual packet transmission from one module to another within a single program image. Representing virtual and physical ports interchangeably and embodying their routing relations in runtime data structures makes it possible to produce object modules that can be deployed in a variety of roles without recompilation. We describe a fielded system that combines (a) application virtual ports, (b) a software tool for specifying packet routing to virtual and physical ports, (c) an advanced linker that encapsulates routing actions in runtime tables within a single multi-application image, and (d) a table-driven dispatcher that effects control flow and packet routing. We present results that show performance advantages and demonstrate the usability and security benefits of reconfiguring and redeploying programs in object module form.

关键词： packet processing Virtual network port Linking Executable image

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Hardware accelerator to speed up packet processing in NDN router

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COMPUTER COMMUNICATIONS 2016年 91-92卷 109-119页

作者： Yu, Weiwen Pao, Derek City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

A hardware implementation of the pending interest table (PIT) for named data networking (NDN) is presented. One of the major challenges in this research is the per-packet update requirement in NDN packet processing. In general, the data structure of the lookup table is optimized in order to minimize the implementation cost and maximize the lookup performance. However, more computation steps are required to update the highly optimized data structure. Thus, the design of the hardware lookup table needs to tradeoff between the implementation cost, lookup performance and update cost. We employ an on-chip Bloom Filter and an off-chip linear-chained hash table in our design. The lookup operation for an interest/data packet and the associated update operation are integrated into one task. This can effectively reduce the overall processing time and the I/O communications with the software control unit. Our design also incorporates a name ID table (nidT) to store all distinct name IDs (nid) in the PIT. If the content name in an interest packet can be found in the nidT, then the router needs not look up the forwarding information base (FIB) to determine how to forward the interest packet. This can reduce the workload of the FIB significantly. For proof-of-concept, the proposed hardware architecture is implemented on a FPGA and the overall packet processing rate is about 56 to 60 million packets per second. (C) 2016 Elsevier B.V. All rights reserved.

关键词： packet processing Named data networking Hardware lookup table

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HIGH-SPEED packet processing USING RECONFIGURABLE COMPUTING

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IEEE MICRO 2014年第1期34卷 8-18页

作者： Brebner, Gordon Jiang, Weirong Xilinx Labs San Jose CA 95124 USA

THIS ARTICLE PRESENTS A NEW TOOL CHAIN THAT MAPS A DOMAIN-SPECIFIC packet-processing LANGUAGE CALLED PX TO HIGH-PERFORMANCE RECONFIGURABLE-COMPUTING ARCHITECTURES BASED ON FPGA TECHNOLOGY. PX IS A DECLARATIVE LANGUAGE WITH OBJECT-ORIENTED SEMANTICS. A CUSTOMIZED COMPUTING ARCHITECTURE IS GENERATED TO MATCH THE EXACT REQUIREMENTS EXPRESSED IN THE PX DESCRIPTION. THIS ARCHITECTURE IS DYNAMICALLY PROGRAMMABLE VIA CUSTOM FIRMWARE UPDATES WHEN THE packet-processing SYSTEM IS IN OPERATION.

关键词： Computer architecture Computer languages Data communication data communications declarative language domain-specific architectures Field programmable gate arrays OpenFlow packet processing packet switching Program processors programming environments PX Reconfigurable architectures reconfigurable hardware

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A dynamic signaling mechanism based on symbiotic packet processing

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COMPUTER COMMUNICATIONS 2005年第1期29卷 77-92页

作者： Matyasovszki, I Flanagan, C Nelson, J Univ Limerick ECE Dept Limerick Ireland

The Symbiotic packet processing Architecture is a framework for the exploitation of packet header coding redundancy. packet headers show coding redundancy from both a practical and a design perspective. The focus of this paper is on the experimental evaluation of this framework. This is accomplished using the proof of concept design and implementation of a novel in-band, path-coupled signaling protocol for IPv4/IPv6. The implementation of this signaling protocol is being carried out based on the ns2(1) simulator. Ns2 simulation results are then compared with similar RSVP-ns2(2) simulations carried out in identical conditions. Further, simulation results show that while being more lightweight than RSVP, the performance of the in-band signaling protocol presented in this paper is very close if not identical to that of RSVP in ns2. (c) 2005 Elsevier B.V. All rights reserved.

关键词： signaling QoS packet processing multiprotocol

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Trading packet headers for packet processing

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IEEE-ACM TRANSACTIONS ON NETWORKING 1996年第2期4卷 141-152页

作者： Chandranmenon, GP Varghese, G Dept. of Comput. Sci. Washington Univ. St. Louis MO USA

In high speed networks, packet processing is relatively expensive while bandwidth is cheap. Thus, it pays to add information to packet headers to make packet processing easier. While this is an old idea, we describe several specific new mechanisms based on this principle, We describe a new technique, source hashing, which can provide O(1) lookup costs at the data link, routing, and transport layers, Source hashing is especially powerful when combined with the old idea of a flow identifier (flow ID);the pow ID allows packet processing information to be cached and source hashing allows efficient cache lookups. Unlike virtual circuit identifiers (VCI's), source hashing does not require a round-trip delay for set up, In an experiment with the BSD packet filter implementation, we found that adding a flow ID and a source hash improved packet processing costs by a factor of seven, We also found a 45% improvement when we conducted a similar experiment with IP packet forwarding, We also describe two other new techniques: threaded indices, which allows fast VCI-like lookups for datagram protocols like IP;and a Data Manipulation Layer (DML), which compiles out all the information needed for integrated layer processing (ILP) and scheduling into an easily accessible portion of each packet.

关键词： .TRANSACTIONS ON NETWORKING datagram packet processing round-trip adding data link indices identifier Headers Trading packet source hashing Sourcehashing processing information packet filter

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