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parallel compilation - DESIGN AND ITS APPLICATION TO SIMULA 67

COMPUTER LANGUAGES 1978年第2期3卷 75-94页

作者： SCHWARTZ, RL Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena CA 91103 U.S.A. Computer Science Department University of California Los Angeles CA 90024 U.S.A.

A design for a separate compilation facility for the SIMULA 67 programming language is presented. The paper explores the problems with existing separate compilation schemes, and proposes a new scheme that allows top-down, bottom-up, or even parallel development and integration of program modules. An evaluation of the proposal and a discussion of its applicability to other languages are then given.

关键词： SIMULA 67 Programming language design Separate compilation parallel compilation Module

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Automatic communication code generation in parallel compilation system

Automatic communication code generation in parallel compilat...

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2006年国际电子、工程及科学领域的分布式计算和应用学术研讨会

作者： Xue-rong GONG1,Yong-hong SHENG2,Ping ZHANG3 National Digital Switching System Engineering &Technological R&D Center Zhengzhou,Henan CHINA Lin-sheng LU Jiangnan Institute of Computing Technology Wuxi,Jiangsu CHINA

The paper introduces computation decomposition and dependence relation in parallel compilation,and presents how to generate communication code automatically according to data and computation decomposition as well as dependence *** communication code consists of four parts:data distribution,communication before computation,synchronization communication,and data *** founding different linear inequalities system and using FME method,we can create communication loop nest and insert MPI send and receive code into the loop nest. One linear inequalities system,used to create the code of data distribution and data gathering,is made up of data decomposition and the bound of the *** linear inequalities system,used to create the communication code before computation and the synchronization communication code,is made up of computation and data decomposition, data dependence relation,and the bound of *** paper also presents several methods of communication optimization.

关键词： parallel compilation linear inequalities system code generation LWT communication optimization

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parallel RECOGNITION AND PARSING ON MESH-CONNECTED COMPUTERS WITH MULTIPLE BROADCASTING

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COMPUTER LANGUAGES 1994年第1期20卷 43-51页

作者： PRADEEP, B MURTHY, CSR INDIAN INST TECHNOL DEPT COMP SCI & ENGNMADRAS 600036TAMIL NADUINDIA TATA INFORMAT SYST LTD BANGALORE 560017INDIA

In this paper we present an optimal linear time algorithm for recognition and parsing of context-free languages on n x n mesh connected computers with multiple broadcasting, for an input string of length n. Our algorithm is based on the well-known Cocke-Younger-Kasami (CYK) algorithm for the recognition and parsing of context-free languages, and is faster than two recent algorithms available in the literature. The parallel recognition of context-free languages is of particular importance since parallel compilation is an increasingly important application because of the availability of parallel hardware and the long running times of optimizing and parallelizing compilers. Our algorithm is a contribution towards this end.

关键词： CYK ALGORITHM MULTIPLE BROADCASTING RECOGNITION PARSING parallel compilation CONTEXT-FREE GRAMMARS CONTEXT-FREE LANGUAGES

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PROGRAM STRUCTURE AS BASIS FOR THE parallelIZATION OF GLOBAL REGISTER ALLOCATION

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COMPUTER LANGUAGES 1993年第2期19卷 135-155页

作者： ZOBEL, A School of Computer Science Carnegie Mellon University Pittsburgh PA 15213 U.S.A.

We propose a model for global register allocation via graph coloring that uses knowledge about program structure to guide global register allocation. We define restrictions that must be met by the live ranges of loops and conditionals such that the corresponding portions of the register conflict graph are interval graphs. This knowledge is used to locate clique separators in register conflict graphs. We discuss how clique separators can be used both to improve sequential register allocation and as a a platform for parallelized global register allocation. We conclude this paper by presenting measurements for a benchmark of C kernels for most of which our method found all clique separators.

关键词： parallel compilation HIERARCHICAL GLOBAL REGISTER ALLOCATION CLIQUE SEPARATORS parallel GLOBAL REGISTER ALLOCATION GRAPH COLORING

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HIERARCHICAL compilation OF MACRO DATA-FLOW GRAPHS FOR MULTIPROCESSORS WITH LOCAL MEMORY

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1994年第7期5卷 720-736页

作者： PRASANNA, GNS AGARWAL, A MUSICUS, BR MIT COMP SCI LABCAMBRIDGEMA 02139 MIT ELECTR RES LABCAMBRIDGEMA 02139

This paper presents a hierarchical approach for compiling macro dataflow graphs for multiprocessors with local memory. Macro dataflow graphs comprise several nodes (or macro operations) that must be executed subject to prespecified precedence constraints. Programs consisting of multiple nested loops, where the precedence constraints between the loops are known, can be viewed as macro dataflow graphs. The hierarchical compilation approach comprises a processor allocation phase followed by a partitioning phase. In the processor allocation phase, using estimated speedup functions for the macro nodes, computationally efficient techniques establish the sequencing and parallelism of macro operations for close-to-optimal run-times. The second phase partitions the computations in each macro node to maximize communication locality for the level of parallelism determined by the processor allocation phase. The same approach can also be used for programs consisting of multiple-loop nests, when each of the nested loops can be characterized by a speedup function. These ideas have been implemented in a prototype structure-driven compiler, SDC, for expressions of matrix operations. The paper presents the performance of the compiler for several matrix expressions on a simulator of the Alewife multiprocessor.

关键词： parallel PROCESSING parallel compilation parallelIZING COMPILERS COMMUNICATION LOCALITY TASK SCHEDULING DISTRIBUTED-MEMORY MULTIPROCESSORS CACHE-COHERENT MULTIPROCESSORS

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MODEL, DESIGN, AND EVALUATION OF A COMPILER FOR A parallel PROCESSING ENVIRONMENT

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1977年第6期3卷 394-405页

作者： BAER, JL ELLIS, CS UNIV WASHINGTON DEPT COMP SCISEATTLEWA 98195

The problem of designing compilers for a multiprocessing environment is approached. We show that by modeling an existing sequential compiler, we gain an understanding of the modifications necessary to transform the sequential structure into a pipeline of processes. The pipelined compiler is then evaluated through measurements and simulation. Properties of the model, a generalized Petri Net, are also discussed.

关键词： Petri Nets Design Methodology Measurements And Simulation parallel compilation parallel Processing

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compilation On The GPU? A Feasibility Study 22

Compilation On The GPU? A Feasibility Study

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19th ACM International Conference on Computing Frontiers (CF)

作者： Voetter, Robin F. Huijben, Marcel Rietveld, Kristian F. D. Leiden Univ LIACS Leiden Netherlands

ISBN: (纸本)9781450393386

The emergence of highly parallel architectures has led to a renewed interest in parallel compilation. In particular, the widespread availability of GPU architectures raises the question whether compilation on the GPU is feasible. In this paper, we describe the first design and implementation of a parallel compiler from a simple imperative programming language to RISC-V machine code, that is fully executed on a GPU. To accomplish this, all stages from parsing to machine code generation were redesigned to exploit fine-grained parallelism. Experimental evaluation of the implemented prototype demonstrates our proposed parallel techniques to be effective and implementation of compilation on the GPU to be feasible. Finally, we propose a number of avenues for future work and hope to revitalize research into parallel compilation conducted in the 1980s.

关键词： parallel compilation GPUs Compiler Construction Parsing Code Generation

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Reducing FPGA Compile Time with Separate compilation for FPGA Building Blocks 18

Reducing FPGA Compile Time with Separate Compilation for FPG...

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International Conference on Field-Programmable Technology (ICFPT)

作者： Xiao, Yuanlong Park, Dongjoon Butt, Andrew Giesen, Hans Han, Zhaoyang Ding, Rui Magnezi, Nevo Rubin, Raphael DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (纸本)9781728129433

Today's FPGA compilation is slow because it compiles and co-optimizes the entire design in one monolithic mapping flow. This achieves high quality results but also means a long edit-compile-debug loop that slows development and limits the scope of design-space exploration. We introduce PRflow that uses partial reconfiguration and an overlay packet-switched network to separate the HLS-to-bitstream compilation problem for individual components of the FPGA design. This separation allows both incremental compilation, where a single component can be recompiled without recompiling the entire design, and parallel compilation, where all the components are compiled in parallel. Both uses reduce the compilation time. Mapping the Rosetta Benchmarks to a Xilinx XCZU9EG, we show compilation times reduce from 42 minutes to 12 minutes (one case from 160 minutes to 18 minutes) when running on top of commercial tools from Xilinx. Using Symbiflow (Project X-Ray/Yosys/VPR), we show preliminary evidence we can further reduce most compile times under 5 minutes, with some components mapping in less than 2 minutes.

关键词： Divide and conquer Fast compilation Fast mapping FPGA Incremental compilation parallel compilation Partial reconfiguration

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Call Sequence Prediction through Probabilistic Calling Automata 14

Call Sequence Prediction through Probabilistic Calling Autom...

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2014 ACM International Conference on Object-Oriented-Programming-Systems-Languages-and-Applications (OOPSLA 14)

作者： Zhao, Zhijia Wu, Bo Zhou, Mingzhou Ding, Yufei Sun, Jianhua Shen, Xipeng Wu, Youfeng Coll William & Mary Williamsburg VA 23187 USA Colorado Sch Mines Golden CO 80401 USA N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781450325851

Predicting a sequence of upcoming function calls is important for optimizing programs written in modern managed languages (e.g., Java, Javascript, C#.) Existing function call predictions are mainly built on statistical patterns, suitable for predicting a single call but not a sequence of calls. This paper presents a new way to enable call sequence prediction, which exploits program structures through Probabilistic Calling Automata (PCA), a new program representation that captures both the inherent ensuing relations among function calls, and the probabilistic nature of execution paths. It shows that PCA-based prediction outperforms existing predictions, yielding substantial speedup when being applied to guide Just-In-Time compilation. By enabling accurate, efficient call sequence prediction for the first time, PCA-based predictors open up many new opportunities for dynamic program optimizations.

关键词： Languages Performance Function call Call sequence prediction Probabilistic calling automata Dynamic optimizations Just-in-time compilation parallel compilation

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A Multi-threaded Fast Hardware Compiler for HDLs 2023

A Multi-threaded Fast Hardware Compiler for HDLs

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32nd ACM SIGPLAN International Conference on Compiler Construction (CC)

作者： Wang, Sheng-Hong Coffman, Hunter James Mayer, Kenneth Garg, Sakshi Renau, Jose UC Santa Cruz Santa Cruz CA 95064 USA

ISBN: (纸本)9798400700880

A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer's productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in compilation technology is limited. We design and implement LiveHD, a new multi-threaded, fast, and generic compilation framework across many HDLs (FIRRTL, Verilog, and Pyrope). We propose new parallel full and bottom-up passes to handle HDLs. The resulting compiler can parallelize all the compiler steps. LiveHD can achieve 5.5x scalability speedup when elaborating a CHISEL RISC-V Manycore. It also gets from 7.7x to 8.4x scalability speedup for a benchmark designed in all three HDLs. This is achieved with a fast single-threaded LiveHD baseline with 6x speedup compared to compilers such as Scala-FIRRTL and 8.6x against Yosys on Verilog.

关键词： HDL Compiler Design parallel compilation

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