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INTERNATIONAL JOINT CONF ON NEURAL NETWORKS ( IJCNM-90 )

作者： WILSON, CL WILKINSON, RA GARRIS, MD Nat Inst of Standards & Technol Gaithersburg MD USA

Two neural-network-based methods are combined to develop font-independent character recognition on a distributed array processor. Feature localization and noise reduction are achieved using least-squares optimized Gabor filtering. The filtered images are then presented to an ART-1-based learning algorithm which produces self-organizing sets of neural network weights used for character recognition. Implementation of these algorithms on a highly parallel computer with 1024 processors allows high-speed character recognition to be achieved in 8 ms/image with greater than 99 % accuracy on machine print and 80 % accuracy on unconstrained hand-printed characters

关键词： feature localization neural-network-based methods font-independent character recognition distributed array processor noise reduction least-squares optimized Gabor filtering filtered images ART-1-based learning algorithm self-organizing sets neural network weights parallel computer hand-printed characters character recognition learning systems neural nets parallel algorithms

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Program analysis in the compiler of a parallel computer

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Cybernetics 1979年第1期15卷 100-103页

作者： Pronina, V.A.

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REX: A reconfigurable experimental system for evaluating parallel computer systems

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2003年第10期E86D卷 2016-2024页

作者： Kodama, Y Katashita, T Sayano, K Natl Inst Adv Ind Sci & Technol Tsukuba Ibaraki 3058568 Japan

REX is a reconfigurable experimental system for evaluating and developing parallel computer systems. It consists of large-scale FPGAs, and enables the systems to be reconfigured from their processors to the network topology in order to support their evaluation and development. We evaluated REX using several implementations of parallel computer systems, and showed that it had enough scalability of gates, memory throughput and network throughput. We also showed that REX was an effective tool because of its emulation speed and reconfigurability to develop systems.

关键词： emulation parallel computer reconfigurable scalable

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REALIZATION OF A NEURAL NETWORK MODEL NEOCOGNITRON ON A HYPERCUBE parallel computer

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International Journal of High Speed Computing 1990年第1期2卷 1-16页

作者： TAKAYUKI ITO KUNIHIKO FUKUSHIMA SEI MIYAKE Visual Science Research Division NHK Science and Technical Research Laboratories 1–10–11 Kinuta Setagaya-ku Tokyo 157 Japan Present address: Department of Biophysical Engineering Faculty of Engineering Science Osaka University Toyonaka Osaka 560 Japan. ATR Auditory and Visual Perception Research Laboratory Sanpeidani Inuidani Seika-cho Soraku-gun Kyoto-fu 619–02 Japan Present address: Visual Science Research Division NHK Science and Technical Research Laboratories 1–10–11 Kinuta Setagaya-ku Tokyo 157 Japan.

The Neocognitron, a neural network model which has a multilayered structure, has been realized on a hypercube parallel computer, NCUBE. The structure of the Neocognition was analyzed and discussed from the point of view of parallel processing. An efficient node-assignment has been made with full consideration of the network structure of the Neocognitron and the properties of the hypercube machine. Eight Neocognitron systems, each of which can recognize a handwritten numeral, have been achieved on the NCUBE which has 512 nodes. Broadcast and gathering method, which realizes exhaustive connections among cells, was proposed and its performance discussed.

关键词： neural network parallel computer character recognition

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Application of domain decomposition to simulation of oil recovery on a parallel computer

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Journal of the Institution of Engineers (India): Chemical Engineering Division 2001年第1期82卷 24-29页

作者： Sheorey, T. Muralidhar, K. Department of Mechanical Engineering Indian Institute of Technology Kanpur 208 016 India

Numerical simulation of oil recovery from a layered porous formation is discussed in this article. A mathematical model of oil-water flow in the porous medium in terms of the phase pressures has been presented. A fully implicit nonlinear coupled approach with a five-point central difference scheme has been used to solve the governing equations. On physical domains of practical interest, the oil recovery simulation becomes computationally intensive in terms of the CPU time and memory. To alleviate this difficulty, a parallel computing strategy, based on domain decomposition, has been evaluated in the present study. During domain decomposition, the original problem is solved independently in a set of subdomains that are obtained by partitioning the full physical domain. Two interface matching techniques that enforce the necessary continuity conditions at the interfaces of the subdomains have been applied in the present study. These are based on the Schwarz and the Uzawa algorithms. Results show a uniform speed-up in CPU time and a proportional reduction in the memory on up to 28 processors. A second technique, based on data parallelism where the full matrix, is inverted in parallel across all the available processors is not found to be effective.

关键词： Domain decomposition technique parallel computer Simulation of oil recovery

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SORTING ON A MESH-CONNECTED parallel computer

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COMMUNICATIONS OF THE ACM 1977年第4期20卷 263-271页

作者： THOMPSON, CD KUNG, HT CARNEGIE MELLON UNIV DEPT COMP SCIPITTSBURGHPA 15213

Presents the algorithms for sorting the n[sup 2] elements on an n X n mesh-connected processor array requiring O (n) routing and comparison steps. Characteristics of the algorithms; Application of the algorithms for ILLIAC IV-type parallel computers; Development of efficient sorting algorithms for interconnection patterns; Concept of sorting problem.

关键词： parallel computer parallel merge parallel sorting perfect shuffle processor interconnection pattern routing and comparison steps

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Ten ways to waste a parallel computer 09

Ten ways to waste a parallel computer

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Proceedings of the 36th annual international symposium on computer architecture

作者： Katherine Yelick University of California at Berkeley Berkeley CA USA

ISBN: (纸本)9781605585260

As clock speed increases taper off and hardware designers struggle to scale parallelism within a chip, software developers and researchers must face the challenge of writing portable software with no clear architectural target. On the hardware side, energy considerations will dominate many of the design decisions, and will ultimately limit what systems and applications can be built. This is especially true at the high end, where the next major milestone of exascale computing will be unattainable without major improvements in *** hardware designers have long worried about the efficiency of their designs, especially for battery-operated devices, software developers in general have not. To illustrate this point, I will describe some of the top ways to waste time and therefore energy waiting for communication, synchronization, or interactions with users or other systems. Data movement, rather than computation, is the big consumer of energy, yet software often moves data up and down the memory hierarchy or across a network multiple times. At the same time, hardware designers need to take into account the constraints of the computational problems that will run on their systems, as a design that is poorly matched to the computational requirements will end up being inefficient. Drawing on my own experience in scientific computing, I will give examples of how to make the combination of hardware, algorithms and software more efficient, but also describe some of the challenges that are inherent in the application problems we want to solve. The community needs to take an integrated approach to the problem, and consider how much business or science can be done per Joule, rather than optimizing a particular component of the system in isolation. This will require rethinking the algorithms, programming models, and hardware in concert, and therefore an unprecedented level of collaboration and cooperation between hardware and software designers.

关键词： parallel computer energy

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A universal, dynamically adaptable and programmable network router for parallel computers

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VLSI DESIGN 2001年第1期12卷 25-52页

作者： Golota, TI Ziavras, SG New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA New Jersey Inst Technol CIS Dept Newark NJ 07102 USA

Existing message-passing parallel computers employ routers designed for a specific interconnection network and deal with fixed data channel width. There are disadvantages to this approach, because the system design and development times are significant and these routers do not permit run time network reconfiguration. Changes in the topology of the network may be required for better performance or fault-tolerance. In this paper, we introduce a class of high-performance universal (statically and dynamically adaptable) programmable routers (UPRs) for message-passing parallel computers. The universality of these routers is based on their capability to adapt at run and/or static times according to the characteristics of the systems and/or applications. More specifically, the number of bidirectional data channels, the channel size and the I/O port mappings (for the implementation of a particular topology) can change dynamically and statically. Our research focuses on system-level specification issues of the UPRs, their VLSI design and their simulation to estimate their performance. Our simulation of data transfers via UPR routers employs VHDL code in the Mentor Graphics environment. The results show that the performance of the routers depends mostly on their current configuration. Details of the simulation and synthesis are presented.

关键词： parallel computer message-passing computer message routing hardware router universal router adaptable router

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Simulation of Linear Displacement Experiments on Massively parallel computers

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SPE JOURNAL 1996年第3期1卷 327-340页

作者： Lee, S. H. Padmanabhan, L. Al-Sunaidi, H. A. Chevron Petr Technol Co POB 446 La Habra CA 90633 USA Saudi Aramco Dhahran Saudi Arabia

We have developed a throat-bulb network model to simulate multiphase flow experiments. The model has been efficiently implemented on massively parallel computers (MasPar and CM5). This model has allowed us to study the dynamics of displacement processes. Using grids of size 64 x 64 x 128 (half a million cells), we are able to incorporate random variations in the throat and pore size distributions and observe flow patterns such as viscous fingering, stable front displacement, and invasion percolation. Furthermore, we are able to discern certain scaling rules in terms of macroscale variables. Displacement processes in a network model with random distribution of throat and pore size can be characterized by three parameters: M (viscosity ratio), Ca (capillary number), and Cg (the ratio of capillary number and Bond number). Macroscale variables, K-r and S-or, are strongly dependent on flow patterns, whereas the dynamic capillary pressure, P-c, is independent of flow patterns. Analysis of laboratory measurements of these macroscopic variables is generally based on steady state approximations and moreover, it offers no clue as to how one might extrapolate the results to the reservoir scale. Using the pore network simulator, we can model dynamic flow behavior and understand the scaling rules for experimental measurements. The simulator will eventually become a practical tool to investigate multi-phase flow in various flow conditions. Furthermore, a better understanding of experimental measurements will help us construct effective grid-block properties for reservoir simulation.

关键词： pore fluid dynamics relative permeability residual saturation network model upstream oil & gas parallel computer reservoir simulation capillary force saturation Flow in porous media Formation Evaluation & Management Improved and Enhanced Recovery Information Management and Systems Production logging Reservoir Characterization Reservoir Fluid Dynamics Reservoir Simulation Well & Reservoir Surveillance and Monitoring

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Analytic modeling of updating based Cache coherent parallel computers

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1998年第6期E81D卷 504-512页

作者： Joe, K Fukuda, A Wakayama Univ Fac Syst Engn Wakayama 6408441 Japan

In this paper, we apply the Semi-markov Memory and Cache coherence Interference (SMCI) model, which we had proposed for invalidating based cache coherent parallel computers, to an updating based protocol. The model proposed here, the SMCI/Dragon model, can predict performance of cache coherent parallel computers with the Dragon protocol as well as the original SMCI model for the Synapse protocol. Conventional analytic models by stochastic processes to describe parallel computers have the problem of numerical explosion in the number of states necessary as the system size increases. We have already shown that the SMCI model achieved both the small number of states to describe parallel computers with the Synapse protocol and the inexpensive computation cost to predict their performance. In this paper, we demonstrate generality of the SMCI model by applying it to the another cache coherence protocol, Dragon, which has opposite characteristics than Synapse. We show the number of states required by constructing the SMCI/Dragon model is only 21 which is as small as SMCI/Synapse, and the computation cost is also the order of microseconds. Using the SMCI/Dragon model, we investigate several comparative experiments with widely known simulation results. We found that there is only a 5.4% differences between the simulation and the SMCI/Dragon model.

关键词： parallel computer performance prediction analytic model Cache coherence

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