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RECONFIGURABLE parallel computer architecture BASED ON WAVELENGTH-DIVISION MULTIPLEXED OPTICAL INTERCONNECTION NETWORK

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parallel Processing Letters 1992年第2N03期2卷 117-127页

作者： KHALED A. ALY PATRICK W. DOWD Department of Electrical and Computer Engineering State University of New York at Buffalo Buffalo NY 14260 USA This work was supported by the National Science Foundation under Grants CCR-9010774 and ECS-9112435.

Reconfigurability is a desirable characteristic in parallel computer architecture that supports the structural parallelism inherent to multiple parallel algorithms. This paper presents a novel approach to achieve reconfigurability via a multiple-domain wavelength-division multiplexed optical interconnection network. A network structure is defined to host a set of point-to-point guest interconnection topologies. Fast complete reconfiguration takes place by re-labeling node identifiers and re-tuning receiver filters according to a local table at each node. For a network of size N, the connecting fiber complexity is O(N), the same order of the link complexities of the individual topologies. The proposed network avoids the possible edge dilation, congestion, and cumulative switching latencies associated with previously proposed approaches.

关键词： parallel computer architecture reconfigurability interconnection networks virtual topology optical interconnection

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LATTICE GAUGE-THEORY WITH A FAST HIGHLY parallel computer

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JOURNAL OF STATISTICAL PHYSICS 1986年第5-6期43卷 1061-1072页

作者： CHRIST, NH 1.Department of Physics Columbia University 10027 New York New York

Results for the temperature of the color deconfinement phase transition in pure SU(3) lattice gauge theory are described. These were obtained on a specially built 16-node, 256 Megaflop computer using the Metropolis al... 详细信息

关键词： parallel computer architecture lattice gauge theory quantum chromodynamics deconfinement phase transition

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Alleviating consumption channel bottleneck in wormhole-routed k-ary n-cube systems

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1998年第5期9卷 481-496页

作者： Basak, D Panda, DK FORE Syst Inc Warrendale PA 15086 USA Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA

This paper identifies performance degradation in wormhole routed k-ary n-cube networks due to limited number of router-to-processor consumption channels at each node. Many recent research in wormhole routing have advocated the advantages of adaptive routing and virtual channel flow control schemes to deliver better network performance. This paper indicates that the advantages associated with these schemes cannot be realized with limited consumption capacity. To alleviate such performance bottlenecks, a new network interface design using multiple consumption channels is proposed. To match virtual multiplexing on network channels, we also propose each consumption channel to support multiple virtual consumption channels. The impact of message arrival rate at a node on the required number of consumption channels is studied analytically. It is shown that wormhole networks with higher routing adaptivity, dimensionality, degree of hot-spot traffic, and number of virtual lanes have to take advantage of multiple consumption channels to deliver better performance. The interplay between system topology, routing algorithm, number of virtual lanes, messaging overheads, and communication traffic is studied through simulation to derive the effective number of consumption channels required in a system. Using the ongoing technological trend, it is shown that wormhole-routed systems can use up to two-four consumption channels per node to deliver better system performance.

关键词： parallel computer architecture wormhole routing k-ary n-cube consumption channel virtual channel deterministic routing adaptive routing hot-spot traffic and interprocessor communication

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State-of-the-art in heterogeneous computing

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SCIENTIFIC PROGRAMMING 2010年第1期18卷 1-33页

作者： Brodtkorb, Andre R. Dyken, Christopher Hagen, Trond R. Hjelmervik, Jon M. Storaasli, Olaf O. SINTEF ICT Dept Appl Math N-0314 Oslo Norway Oak Ridge Natl Lab Future Technol Grp Oak Ridge TN USA

Node level heterogeneous architectures have become attractive during the last decade for several reasons: compared to traditional symmetric CPUs, they offer high peak performance and are energy and/or cost efficient. With the increase of fine-grained parallelism in high-performance computing, as well as the introduction of parallelism in workstations, there is an acute need for a good overview and understanding of these architectures. We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs). We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms. Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.

关键词： Power-efficient architectures parallel computer architecture stream or vector architectures energy and power consumption microprocessor performance

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Energy-efficient multithreading for a hierarchical heterogeneous multicore through locality-cognizant thread generation

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2013年第12期73卷 1551-1562页

作者： La Fratta, Patrick A. Kogge, Peter M. US Army Res Dev & Engn Ctr RDECOM Aviat & Missile Res Dev & Engn Ctr AMRDEC RDMR WDG C Bldg 5400 Redstone Arsenal AL 35898 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

Energy costs have become increasingly problematic for high performance processors, but the rising number of cores on-chip offers promising opportunities for energy reduction. Further, emerging architectures such as heterogeneous multicores present new opportunities for improved energy efficiency. While previous work has presented novel memory architectures, multithreading techniques, and data mapping strategies for reducing energy, consideration to thread generation mechanisms that take into account data locality for this purpose has been limited. This study presents methodologies for the joint partitioning of data and threads to parallelize sequential codes across an innovative heterogeneous multicore processor called the Passive/Active Multicore (PAM) for reducing energy consumption from on-chip data transport and cache access components while also improving execution time. Experimental results show that the design with automatic thread partitioning offered reductions in energy-delay product (EDP) of up to 48%. Published by Elsevier Inc.

关键词： parallel computer architecture Heterogeneous multicore Energy-efficient processor design

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A system for evaluating performance and cost of SIMD array designs

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2000年第2期60卷 217-246页

作者： Herbordt, MC Cravy, J Sam, R Kidwai, O Lin, C Univ Houston Dept Elect & Comp Engn Houston TX 77204 USA

SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the efficient evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The underlying issues include the size of the architecture space. the lack of portability of the test programs, and the inherent complexity of simulating up to hundreds of thousands of processing elements. The overall method we use is to combine architecture level and Electronic Design Automation (EDA) level modeling by using an EDA-based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture level simulator but it also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. The particular problem of computational cost of the architectural level simulation is addressed with a novel approach to trace-based simulation (we call it trace compilation), which we find to be one to two orders of magnitude faster than instruction level simulation while still retaining much of the accuracy of the model. Furthermore, traces must be generated for only a small fraction of the possible parameter combinations. Using trace compilation also addresses program portability by allowing the user to code in a single data parallel language with a single compiler, regardless of the target architecture. We have used our system to evaluate thousands of potential SIMD array designs with respect to real applications and present some Sample results. (C) 2000 Academic Press.

关键词： SIMD architecture parallel computer architecture computer design evaluation computer simulation domain specific systems virtual prototyping

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HIERARCHICAL SCALABLE PHOTONIC architectureS FOR HIGH-PERFORMANCE PROCESSOR INTERCONNECTION

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IEEE TRANSACTIONS ON computerS 1993年第9期42卷 1105-1120页

作者： DOWD, PW BOGINENI, K ALY, KA PERREAULT, JA Dept. of Electr. & Comput. Eng. State Univ. of New York Buffalo NY USA

This paper introduces two hierarchical optical structures for processor interconnection and compares their performance through analytic models and discrete-event simulation. Both architectures are based on wavelength division multiplexing (WDM) which enables multiple multi-access channels to be realized on a single optical fiber. The objective of the hierarchical architectures is to achieve scalability yet avoid the requirement of multiple wavelength tunable devices per node. Furthermore, both hierarchical architectures are single-hop: a packet remains in the optical form from source to destination and does not require cross dimensional intermediate routing. The first structure is physically hierarchical but wavelength flat: all nodes share the same wavelength space. The second structure is a wavelength multiplexed hierarchical structure with wavelength channel re-use at each level, allowing it to be scaled to very large system sizes. It employs acoustooptic tunable filters in conjunction with passive couplers to partition the traffic between different levels of the hierarchy without electronic intervention. An advantage of the second structure is its ability to dynamically vary the bandwidth provided to different levels of the hierarchy. The architectures are compared in terms of complexity and performance scalability.

关键词： parallel computer architecture PROCESSOR INTERCONNECTION OPTICAL FIBER COMMUNICATION WAVELENGTH DIVISION MULTIPLEXING

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Designing communication strategies for heterogeneous parallel systems

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parallel COMPUTING 1998年第14期24卷 2035-2052页

作者： Prakash, R Panda, DK Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA Univ Texas Comp Sci Program Richardson TX 75083 USA

This paper explores the suitability of the emerging passive star-coupled optical interconnection using wavelength division multiplexing as the system interconnect to provide high bandwidth (Gbits/sec) communication demanded by heterogeneous systems. Several different communication strategies (combinations of communication topologies and protocols) are investigated under a representative master-slave computational model. The interplay between system speed, network speed, task granularity, and degree of parallelism is studied using both analytical, modeling and simulations. It is shown that a hierarchical ALOHA-based communication strategy between the master and the slaves, implemented on top of the passive star-coupled:network, leads to a considerable reduction in channel contention and provides 50-80% reduction in task completion time for applications with medium to high degrees of coarse grain parallelism. Comparable reduction in channel contention is also shown to be achieved by using tunable acoustooptic filters at master nodes. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： parallel computer architecture heterogeneous parallel systems hierarchical interconnection optic fiber networks meta-parallelism

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Implementing multidestination worms in switch-based parallel systems: Architectural alternatives and their impact

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2000年第8期11卷 794-812页

作者： Sivaram, R Stunkel, CB Panda, DK IBM Corp Enterprise Syst Grp Poughkeepsie NY 12601 USA IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA

Multidestination message passing has been proposed as an attractive mechanism for efficiently implementing multicast and other collective operations on direct networks. However, applying this mechanism to switch-based parallel systems is nontrivial. In this paper, we propose alternative switch architectures with differing buffer organizations to implement multidestination worms on switch-based parallel systems. First, we discuss issues related to such implementation (deadlock-freedom, replication mechanisms, header encoding, and routing). Next, we demonstrate how an existing central-buffer-based switch architecture supporting unicast message passing can be enhanced to accommodate multidestination message passing. Similarly, implementing multidestination worms on an input-buffer-based switch architecture is discussed, and two architectural alternatives are presented that reduce the wiring complexity in a practical switch implementation. The central-buffer-based and input-buffer-based implementations are evaluated against each other, as well as against the corresponding software-based schemes. Simulation experiments under a range of traffic (multiple multicast, bimodal, varying degree of multicast, and message length) and system size are used for evaluation. The study demonstrates the superiority of the central-buffer-based switch architecture. It also indicates that under bimodal traffic the central-buffer-based hardware multicast implementation affects background unicast traffic less adversely compared to a software-based multicast implementation. These results show that multidestination message passing can be applied easily and effectively to switch-based parallel systems to deliver good multicast and collective communication performance.

关键词： parallel computer architecture switch/router architecture wormhole switching cut-through switching multicast broadcast collective communication interconnection networks performance evaluation

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THE SERIAL PERFORMANCE STANDARDS FOR THE BBS TEST PROGRAMS

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FUTURE GENERATION computer SYSTEMS 1994年第4期10卷 419-428页

作者： RILEY, CP SIMKIN, J Vector Fields Ltd 24 Bankside Kidlington Oxford OX5 1JE UK

ESPRIT Project 5417 - BECAUSE - is concerned with the benchmarking of parallel computer architectures for computer intensive scientific and engineering applications. Fluid flow, semi-conductor modelling and electromagnetic field simulation software was profiled on a range of example applications and sizes. The profiling results were used to select the algorithms and functions that ought to be included in the Because Benchmark Set (BBS). This paper reviews the BBS results obtained on the 'control' sequential architecture computer. The results show consistent performance with some interesting Variations in achieved Mflops.

关键词： BECAUSE BENCHMARK SET PERFORMANCE STANDARDS parallel computer architecture

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