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FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

IEEE ACCESS 2019年 7卷 7823-7859页

作者： Shawahna, Ahmad Sait, Sadiq M. El-Maleh, Aiman King Fahd Univ Petr & Minerals Dept Comp Engn Dhahran 31261 Saudi Arabia King Fahd Univ Petr & Minerals Res Inst Ctr Commun & IT Res Dhahran 31261 Saudi Arabia

Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolutional neural networks (CNNs) have demonstrated their effectiveness in the image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve the desired performance levels. Consequently, hardware accelerators that use application-specific integrated circuits, field-programmable gate arrays (FPGAs), and graphic processing units have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism and their energy efficiency. In this paper, we review the recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in the FPGA-based accelerators of deep learning networks. Thus, this paper is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

关键词： Adaptable architectures convolutional neural networks (CNNs) deep learning dynamic reconfiguration energy-efficient architecture field programmable gate arrays (FPGAs) hardware accelerator machine learning neural networks optimization parallel computer architecture reconfigurable computing

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Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

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computer 2013年第10期46卷 48-55页

作者： Krishna, Tushar Chen, Chia-Hsin Owen Park, Sunghyun Kwon, Woo-Cheol Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shivan MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA MIT Cambridge MA 02139 USA

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reductions in runtime latency and energy expenditure.

关键词： Multicore Processing Radio Mobile System On Chip computer architecture Design Methodology Scalability Ports computers Shared L 2 parallel computer architecture Network On Chip No C Interconnection Network Multicore architecture Scalable Networks Scalability System On Chip So C Cache Coherence Traffic Efficient Network Design On Chip Latency Private L 2

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Dual-mode routing approach for photonic network on chip platforms

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JOURNAL OF SUPERCOMPUTING 2016年第3期72卷 904-925页

作者： Imre, Kayhan M. Hacettepe Univ Dept Comp Engn Ankara Turkey

In this paper, a dual-mode routing approach is proposed for routing messages in 2D photonic network on chip (NoC) platforms. The dual-mode routing approach is based on selecting exclusively one of two routing techniques for each stage of a parallel application. Depending on the data exchange requirements of a specific stage of an application, either a conventional per-message-based routing or a collective routing technique is selected, and the network on chip architecture is organized to support that selection. The network on chip architecture that we use is a two-dimensional torus topology built from novel non-blocking all-port photonic switches. The design of non-blocking all-port photonic switch empowers each node with simultaneous connections to four other nodes in the network. The rich connectivity provided by the switches helps the collective routing technique to efficiently support collective communication operations by allowing deadlock-free and contention-free dense data exchange among the nodes. Similar dense data exchanges are also required for some commonly known parallel algorithms such as parallel matrix multiplication, linear equation solvers and n-body simulation algorithms, just to name a few. A lightweight electronic network is employed for establishing and tearing down the photonic communication paths (light paths) in per-message-based routing technique. The lightweight electronic network is also used for coordinating the whole network in the collective routing technique.

关键词： parallel computing parallel computer architecture Photonic networks Routing Optical circuit switching

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Looping adjacent nodes on multistage interconnection networks

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JOURNAL OF SYSTEMS architecture 1996年第1期42卷 83-93页

作者： Lin, W Chen, EWS Natl Chung-Hsing Univ Taichung Taiwan

Many parallel applications of image processing and linear system problems require multinode broadcasts over a cluster of adjacent nodes of a multi-computer system, In this paper, we propose an efficient solution to the multinode broadcast problem for the multistage interconnection network. Our approach is to connect adjacent nodes through the network to form a loop configuration by which nodes are able to disseminate messages in a highly pipelined fashion. Although barrel shift can achieve loop configurations, it works only in the special case: the length of adjacent nodes is a power of two. Looping adjacent nodes of arbitrary length is still a problem. The difficulty lies in resolving link conflicts that arise from creating paths for loops, We present a procedure for structuring adjacent nodes of variable length into a loop. It first divides a given set of adjacent nodes into two subsets, forming two initial loops on the two subsets. Then it merges the two loops into a single loop without incurring conflicts. In this paper, we also consider looping modulus-adjacent nodes of variable length.

关键词： interconnection networks network communication parallel computer architecture parallel processing

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Efficient multicast on irregular switch-based cut-through networks with up-down routing

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2001年第8期12卷 808-828页

作者： Kesavan, R Panda, DK Network Appliance Inc Sunnyvale CA 94089 USA Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA

The irregular switch-based network of workstations is fast becoming a cost-effective platform for high performance computing. This paper presents efficient multicasting with reduced link contention on irregular switch-based cut-through interconnection using the popular up*/down* (UD) routing and unicast message passing. First, it is proven that, for an arbitrary irregular network with UD routing, it Is not possible to create an ordered list of nodes to implement an arbitrary multicast in a link contention-free manner with a minimal number of communication steps. Next, three different multicast algorithms are proposed with their respective node orderings to reduce link contention: switch-based ordering (SO), switch-based hierarchical ordering (SHO), and chain concatenation ordering (CCO). A variation of the binomial tree-based communication pattern, with unicast message passing, is used on the above orderings to implement multicast. Then, the problem of node contention is described in the case when multiple multicasts occur concurrently in a system. Using source-based information, the CCO algorithm is modified to propose a source-partitioned chain concatenation ordering (SPCCO) algorithm. It is also shown how the SPCCO algorithm reduces the effect of node contention at the cost of link contention. Using detailed simulation experiments, the proposed multicast algorithms are compared with each other as well as with the naive random ordering (RO) algorithm for a range of system sizes, switch sizes, message lengths, input buffer sizes, degrees of connectivity, destination set sizes, and communication start-up times. For the case of single multicast, the CCO algorithm is shown to be the best to Implement multicast with reduced link contention and minimum latency. For the case of multiple multicasts, the SPCCO algorithm is shown to be the best when the start-up overhead dominates the propagation overhead and the CCO algorithm Is shown to be the best otherwise. The results

关键词： parallel computer architecture cut-through routing wormhole routing multicast broadcast collective communication switch-based networks irregular networks networks of workstations

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Efficient broadcast and multicast on multistage interconnection networks using multiport encoding

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1998年第10期9卷 1004-1028页

作者： Sivaram, R Panda, DK Stunkel, CB IBM Power Parallel Syst Poughkeepsie NY 12601 USA Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

This paper proposes a new approach for implementing fast multicast and broadcast in unidirectional and bidirectional multistage interconnection networks (MINs) with multiport encoded multidestination worms. For a MIN with n stages, such worms use n header flits each. One flit is used for each stage of the network and it indicates the output ports to which a multicast message needs to be replicated. A multiport encoded worm with (d(1), d(2)..., d(n), 1 less than or equal to d(i) less than or equal to k) degrees of replication for the respective stages is capable of covering (d(1) x d(2) x...x d(n)) destinations with a single communication start-up. In this paper, a switch architecture is proposed for implementing multidestination worms without deadlock. Three grouping algorithms of varying complexity are presented to derive the associated multiport encoded worms for a multicast to an arbitrary set of destinations. Using these worms, a multinomial tree-based scheme is proposed to implement the multicast. This scheme significantly reduces broadcast/multicast latency compared to schemes using unicast messages. Simulation studies for both unidirectional and bidirectional MIN systems indicate that improvement in broadcast/multicast latency up to a factor of four is feasible using the new approach. Interestingly, this approach is able to implement multicast with reduced latency as the number of destinations increases beyond a certain number. Compared to implementing unicast messages, this approach requires little additional logic at the switches. Thus, the scheme demonstrates significant potential for implementing efficient collective communication operations on current and future MIN-based systems.

关键词： parallel computer architecture collective communication multistage interconnection networks interprocessor communication broadcast multicast wormhole routing virtual cut-through

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WAVELENGTH DIVISION MULTIPLE ACCESS CHANNEL HYPERCUBE PROCESSOR INTERCONNECTION

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IEEE TRANSACTIONS ON computerS 1992年第10期41卷 1223-1241页

作者： DOWD, PW Dept. of Electr. & Comput. Eng. State Univ. of New York Buffalo NY USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A multiprocessor system with a large number of nodes can be built at low cost by combining the recent advances in high capacity channels available through optical fiber communication. A highly fault tolerant system is created with good performance characteristics at a reduction in system complexity. The system capitalizes on the self-routing characteristic of wavelength division multiple access to improve performance and reduce complexity. A hypercube based structure is introduced, where optical multiple access channels span the dimensional axes. This severely reduces the required degree, since only one I/O port is required per dimension. However, good performance is maintained through the high capacity characteristics of optical communication. The reduction in degree is shown to have significant system complexity implications. Four star-coupled configurations are studied as the basis for the optical multiple access channels, three of which exhibit the optical self-routing characteristic. A performance analysis shows that through the integration of agile sources or receivers, and wavelength division multiple access, systems can be developed with significant increases in performance yet at a reduction in communication subsystem complexity.

关键词： computer COMMUNICATION OPTICAL FIBER COMMUNICATION parallel computer architecture WAVELENGTH DIVISION MULTIPLEXING

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The Argus prototype: aggregate use of load modules as a high-density supercomputer

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2006年第15期18卷 1975-1987页

作者： Feng, Xizhou Ge, Rong Cameron, Kirk W. Virginia Polytech Inst & State Univ Dept Comp Sci Blacksburg VA 24061 USA Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

This paper describes the ARGUS prototype, a high-density, low-power supercomputer built from an IXIA network analyzer chassis and load modules. The prototype is configured as a diskless distributed system that is scalable to 128 processors in a single 9U chassis. The entire system has a footprint of 0.25 m(2) (2.5 ft(2)), a volume of 0.09 m(3) (3.3 ft(3)) and maximum power consumption of less than 2200 W. We compare and contrast the characteristics of ARGUS against various machines including our on-site 32-node Beowulf and LANL's Green Destiny. Our results show that the computing density (Gflops ft(-3)) of ARGUS is about 30 times higher than that of the Beowulf and about three times higher than that of Green Destiny with a comparable performance. Copyright (c) 2006 John Wiley & Sons, Ltd.

关键词： performance evaluation high-density computing cluster system parallel and distributed system parallel computer architecture

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NOCA - A Notification-Oriented computer architecture

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IEEE LATIN AMERICA TRANSACTIONS 2015年第5期13卷 1593-1604页

作者： Linhares, R. R. Simao, J. M. Stadzisz, P. C. Univ Tecnol Fed Parana UTFPR Curitiba Parana Brazil

Current software development processes lack techniques for the productive and quality design of software that makes efficient use of the parallel execution capabilities provided by the hardware of modern computing systems. In this context, the Notification Oriented Paradigm (NOP) has been recently developed aiming at a new organization of software logic based on notifications among causal-logical entities. NOP allows exploring the parallelization and/or distribution in a simpler and more efficient way than more commonly used programming paradigms. However, the execution dynamics under the NOP, based on notifications, is not efficiently performed by the hardware of current computing systems. This paper presents a new computer architecture, named NOCA, which is suitable for execution of software developed according to the NOP computing model. NOCA was designed in accordance with the principles of generality and scalability, which allow it to execute NOP software at any level of complexity by fetching it from a program memory. The developed architecture is organized as a fine grain multiprocessor that hierarchically executes instructions through sets of specialized processor cores. Preliminary experiments performed on this architecture show that NOCA presents improvements in terms of performance comparative evaluations.

关键词： Notification-Oriented Paradigm computer Architeture parallel computer architecture

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IMPLICATIONS OF HIERARCHICAL N-BODY METHODS FOR MULTIPROCESSOR architectureS

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ACM TRANSACTIONS ON computer SYSTEMS 1995年第2期13卷 141-202页

作者： SINGH, JP HENNESSY, JL GUPTA, A STANFORD UNIV COMP SYST LABSTANFORDCA 94305

To design effective large-scale multiprocessors, designers need to understand the characteristics of the applications that will use the machines. Application characteristics of particular interest include the amount of communication relative to computation, the structure of the communication, and the local cache and memory requirements, as well as how these characteristics scale with larger problems and machines. One important class of applications is based on hierarchical N-body methods, which are used to solve a wide range of scientific and engineering problems efficiently. Important characteristics of these methods include the nonuniform and dynamically changing nature of the domains to which they are applied, and their use of long-range, irregular communication. This article examines the key architectural implications of representative applications that use the two dominant hierarchical N-body methods: the Barnes-Hut Method and the Fast Multipole Method. We first show that exploiting temporal locality on accesses to communicated data is critical to obtaining good performance on these applications and then argue that coherent caches on shared-address-space machines exploit this locality both automatically and very effectively. Next, we examine the implications of scaling the applications to run on larger machines. We use scaling methods that reflect the concerns of the application scientist and find that this leads to different conclusions about how communication traffic and local cache and memory usage scale than scaling based only on data set size. In particular, we show that under the most realistic form of scaling, both the communication-to-computation ratio as well as the working-set size (and hence the ideal cache size per processor) grow slowly as larger problems are run on larger machines. Finally, we examine the effects of using the two dominant abstractions for interprocessor communication: a shared address space and explicit message passing between pri

关键词： ALGORITHMS EXPERIMENTATION MEASUREMENT PERFORMANCE COMMUNICATION ABSTRACTIONS LOCALITY MESSAGE PASSING N-BODY METHODS parallel APPLICATIONS parallel computer architecture SCALING SHARED ADDRESS SPACE SHARED MEMORY

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