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ELECTRICAL CHARACTERIZATION OF HIGH-SPEED INTERCONNECTS WITH A parallel 3-DIMENSIONAL FINITE-DIFFERENCE TIME-DOMAIN ALGORITHM

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SIMULATION 1995年第5期64卷 289-295页

作者： BATAINEH, A LEE, R OZGUNER, F OHIO STATE UNIV DEPT ELECT ENGNCOLUMBUSOH 43210

Although the Finite Difference Time-Domain (FDTD) method is over 25 years old, its use for the analysis of crosstalk, propagation delay, and pulse distortion of signals on interconnects in high-speed integrated circuits is relatively recent. With the development of faster computers, the use of FDTD has become more widespread because it has shown itself to be an efficient tool for the full-wave modeling of complicated microstrip circuit interconnects. In this paper, we address the parallelization of the FDTD method on multi-dimensional processor meshes mapped onto a hypercube multiprocessor. The use of parallelization is a natural step for the modeling of circuits because of the tremendous computational requirements to simulate even the simplest interconnect geometries. Experimental results on the Intel iPSC/860 hypercube are given which demonstrate a linear speedup in computation time.

关键词： parallel PROCESSING parallel computer architecture TDTD ALGORITHM DIGITAL CIRCUITS S-PARAMETERS

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NOCA - A Notification-Oriented computer architecture: Prototype and Simulator

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IEEE ACCESS 2020年 8卷 37287-37304页

作者： Linhares, Robson R. Pordeus, Leonardo F. Simao, Jean M. Stadzisz, Paulo C. Univ Tecnol Fed Parana UTFPR Grad Program Elect Engn & Ind Informat BR-80230901 Curitiba Parana Brazil Univ Tecnol Fed Parana UTFPR Grad Program Appl Comp BR-80230901 Curitiba Parana Brazil

The Notification Oriented Paradigm (NOP) introduced a new organization of software and hardware logic based on notifications among computational entities. This NOP new organization avoids processing redundancy and allows processing unit decoupling, therefore permitting proper processing performance and processing parallelism/distribution. Thus, the NOP provides means to make efficient use of the parallel execution capabilities of modern computing systems. However, as expected, the execution dynamics of NOP, based on notifications, is not efficiently performed by the hardware of most current computing systems. This paper presents a new solution called Notification-Oriented computer architecture (NOCA), which is suitable for the execution of software developed according to the NOP computing model. The NOCA was designed according to principles of generality and scalability, which allow it to execute NOP software of any size by fetching the application from memory. The proposed architecture is organized as a fine-grained multiprocessor that hierarchically executes instructions through sets of specialized processing cores. Preliminary experiments performed on prototypal FPGA implementation of the NOCA showed the expected behavior of executing NOP applications according to its theoretical computing model. This paper also presents experiments performed on a NOCA simulator extending the scale of parallelization of applications. Results show improvements in maximizing the speedups at higher scales of parallelization, as well as minimizing the effects of processor-to-memory communication bottlenecks by reducing the number of required memory accesses during execution.

关键词： computer architecture notification-oriented paradigm parallel computer architecture computing paradigm

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A hardware accelerator for fault simulation utilizing a reconfigurable array architecture

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VLSI DESIGN 1996年第2期4卷 119-133页

作者： Kang, S Hur, Y Szygenda, SA YONSEI UNIV SEOUL 120749SOUTH KOREA UNIV TEXAS DEPT ELECT & COMP ENGNAUSTINTX 78712

In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurable mesh type processing element (PE) array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell. This new approach provides for a high performance, cost effective, gain over software simulation. Simulation results show that the hardware accelerator is orders of magnitude faster than the software simulation program.

关键词： fault simulation hardware accelerator parallel computer architecture

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Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems

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JOURNAL OF SYSTEMS architecture 2018年 90卷 54-71页

作者： Temucin, Huseyin Imre, Kayhan M. Hacettepe Univ Dept Comp Engn Ankara Turkey

This paper presents a novel scheduling approach that efficiently schedules the computational and the communicational resources of a Software-Defined Photonic Network-on-Chip (SD-PNoC) architecture designed for high-performance real-time systems. The proposed scheduling approach extends the conventional cyclic executive scheduling algorithm from the one that schedules solely the computational resources into a general one that schedules both the computational and the communicational resources together in a synchronized manner. The proposed SD-PNoC architecture employs Software Defined Network (SDN) approach by using application specific conflict-free and contention-free communication patterns to solve the routing and wavelength assignment (RWA) problem exists in photonic networks. The implementations of the collective communication primitives such as broadcast and all-to-broadcast are also presented to demonstrate the system as a whole.

关键词： parallel computer architecture Photonic networks Routing Software defined network Optical circuit switching Real-time systems Cyclic executive scheduling

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INCREASING THE SIZE OF A NETWORK BY A CONSTANT FACTOR CAN INCREASE PERFORMANCE BY MORE THAN A CONSTANT FACTOR

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SIAM JOURNAL ON COMPUTING 1992年第5期21卷 801-823页

作者： KOCH, R MIT DEPT MATHCAMBRIDGEMA 02139 MIT COMP SCI LABCAMBRIDGEMA 02139

The performance of unbuffered routing algorithms for parallel computer architectures is analyzed. Unbuffered algorithms are an alternative to the use of queues. When the capacity of a switch or communications link is exceeded, the extra messages are discarded, and another attempt to transmit the message will be made at a later time. The analysis presented here is relevant for routing on the BBN Butterfly and Agarwal and Knight's Alewife architecture, both of which have interconnection networks based on the butterfly graph. Suppose that each of the N inputs of the butterfly independently decides to send a message with probability p, and that the message is sent to a random output, with each output having an equal probability of being chosen. If more than q messages attempt to traverse an edge, the extra messages over q are discarded. q is called the dilation of the network. The bandwidth is the number of messages that reach their destinations. It is shown that if p = OMEGA((log N)-1/q), the expected bandwidth is THETA(N(log N)-1/q), and if p = o((log N)-1/q), the expected bandwidth is N(p+o(p)). This result also holds for dilated networks based on the d-ary butterfly and for graphs constructed by taking r copies of butterflies and identifying corresponding inputs and also identifying corresponding outputs. An expression is also derived for the asymptotic constants and it is shown that the probability distribution is tightly concentrated about its mean. Interesting techniques are developed for finding asymptotics of nonlinear systems of recurrences. The result may also have implications for design trade-offs since, for sufficiently large networks, having a fixed amount of hardware increasing the value of q will increase bandwidth more than increasing the values of d or r.

关键词： parallel COMPUTATION INTERCONNECTION NETWORK parallel computer architecture PERFORMANCE ANALYSIS DIFFERENCE EQUATIONS

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DISTRIBUTED SIMULATION OF computer-NETWORKS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1990年第1-5期30卷 215-220页

作者： DIRKX, E VERBOVEN, F TIBERGHIEN, J FREE UNIV BRUSSELS DEPT INFOB-1050 BRUSSELSBELGIUM

Complexity and lack of adequate performance evaluation tools for computer networks make them analytically intractable and numerically prohibitive to evaluate. Simulation is therefore the only available evaluation method. Simulation of such complex networks is usually very slow. Using multiple processors appears to be a promising approach. In this paper, the applicability of different general purpose distributed simulation algorithms to the domain of computer network simulation is discussed. Several ways of introducing parallelism are discussed and evaluated.

关键词： Distributed Simulation parallel computer architecture

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Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuit

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1997年第1期44卷 22-40页

作者： Heath, JR Ramamoorthy, S Stroud, CE Hurt, AD UNIV KENTUCKY DEPT COMP SCILEXINGTONKY 40506 CACI INT INC HUNTSVILLEAL 35816

parallel computer architecture systems may be used for real-time data and signal processing applications and may require both static and dynamic load balancing (resource allocation) prior to and during run-time. The literature reveals that each class of parallel computer architecture and its application can require a different approach to static and dynamic load balancing. Common classes of target parallel computer architectures are 1) multiprocessors (shared and distributed memories), 2) distributed processors, and 3) dataflow architectures, This paper addresses a proposed parallel hybrid dataflow architecture, a scalable dynamic load balancing circuit for the proposed architecture, and performance analysis, first, of the load balancing circuit and, second, the architecture using the load balancing circuit, The contributions and focus of this paper are: 1) that it first describes the requirements for and the framework of a parallel, medium to coarse grain, hybrid token controlled dataflow architecture. This paper only deals with real-time applications of the architecture. 2) The paper next describes the dynamic load balancing strategy for the hybrid dataflow architecture and a resulting mathematical model of the load balancing function required by the load balancing strategy. 3) The organization, design, and implementation of a basic digital circuit suitable for VLSI implementation which implements the mathematical model of the load balancing function required by the architecture is next presented. This circuit implements a control token mapping function and is therefore called a ''token mapper.'' 4) It is next shown that the basic dynamic load balancing circuit (token mapper) design if;scalable therefore allowing the hybrid dataflow architecture to be scalable. 5) The performance of the dynamic load balancing circuit is then analyzed at both the circuit and architectural systems level. A parallel simulation of the proposed parallel hybrid dataflow architecture emp

关键词： dataflow computer architectures distributed computer systems dynamic load balancing hybrid dataflow computer architecture multiprocessor computer architectures parallel computer architecture parallel signal processors run-time resource allocation static load balancing task (process) allocation

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Computing requirements of modern medical diagnostic ultrasound machines

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parallel COMPUTING 1998年第9-10期24卷 1407-1431页

作者： Basoglu, C Managuli, R York, G Kim, Y Univ Washington Dept Elect Engn Image Comp Syst Lab Seattle WA 98195 USA

Ultrasound is one of the leading medical imaging modalities because it is safe, noninvasive, portable, easy to use, relatively inexpensive and displays images in real-time. Due to its real-time nature, an ultrasound machine must be able to process its incoming data quickly. High computational and throughput requirements in modern ultrasound machines have restricted their internal design to algorithm-specific hardware with limited programmability. Adding new ultrasound imaging applications or improving a machine's internal algorithms can require costly hardware redesigns and replacements of boards or of the entire machine. In an effort to address these problems, we have reviewed each of the essential functions in modern ultrasound machines and analyzed their computational requirements in programmable systems. These functions include dynamic downconversion, tissue signal processing, color flow processing, scan conversion, and tissue/flow decision. Our estimate of the total computing requirement to current ultrasound machines is 54.71 billion operations per second (BOPS) when transcendental functions are implemented in software and 31.26 BOPS when transcendental functions are implemented in lookup tables taking 160.26 Mbytes of memory. To investigate the feasibility of programmable generalized ultrasound systems, we have designed a flexible and parallel programmable ultrasound processing subsystem, called the Programmable Ultrasound Image Processor (PUIP). As the need for programmable ultrasound machines increases in the future due to various advantages (e.g., lower system cost, faster clinical use and lower research/development expenses), it will be crucial to develop not only a high-performance, scalable, reconfigurable parallel computer architecture meeting the computing requirement, but also efficient ultrasound algorithms that can be optimally mapped into the parallel architecture. (C) 1998 Published by Elsevier Science B.V. All rights reserved.

关键词： ultrasound machines ultrasound computing requirement ultrasound processing algorithms parallel computer architecture programmable ultrasound image processor

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OPSILA - A VECTOR AND parallel PROCESSOR

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IEEE TRANSACTIONS ON computerS 1993年第1期42卷 76-82页

作者： BOERI, F AUGUIN, M Lab. Signaux et Syst. Nice Univ. France

Numerous applications require ever-increasing computational power, which is not provided by sequential computers. The most recent scientific computers combine several schemes of parallelism. These new machines enable efficient implementation of numerous applications that are not straighforwardly achieved due to hardware and software constraints. However, there is still room for more extensive exploitation of the potential parallelism of applications themselves. In this paper, we consider a multiprocessor machine with two operating modes and simple synchronization mechanisms. The operating modes are the vector SIMD mode and the parallel SPMD mode (single program stream, multiple data stream). Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable programming environment, i.e., 1) vector parallelization is performed by the compiler and the hardware and 2) since SPMD parallelization requires mainly the partitioning of the entire set of data, the synchronizations are then often obvious.

关键词： parallel computer architecture SIMD-SPMD MODES VECTOR AND parallel PROCESSING

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COMPRESSED TREE MACHINES

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IEEE TRANSACTIONS ON computerS 1994年第2期43卷 222-225页

作者： ZHENG, SQ Dept. of Comput. Sci. Louisiana State Univ. Baton Rouge LA USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A modified tree architecture called the compressed tree machine is proposed, and it is shown the compressed tree machine can be an alternative to the conventional tree machine.

关键词： parallel computer architecture VLSI LAYOUT TREE STRUCTURE COST/PERFORMANCE TRADE-OFF parallel PROCESSING

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