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MICROPROCESSING AND MICROPROGRAMMING 1989年第2期26卷 139-152页

作者： ROUNCE, PA CHAN, K MACKAY, S STEPTOE, K UNIV LONDON UNIV COLL DEPT COMP SCILONDON WC1E 6BTENGLAND UNIV LONDON UNIV COLL DEPT ELECTR & ELECT ENGNLONDON WC1E 6BTENGLAND

This paper presents the research work in computer architecture currently being undertaken at UCL as part of ESPRIT Project 1588 — the SPAN project. SPAN is concerned with the integration of numeric and symbolic processing on parallel architectures, and involves activities from application software to hardware. A major activity is the development of a common virtual architecture, the Kernel system, to provide a model, parallel architecture for the project. The VLSI architecture work is concerned with investigating possible parallel VLSI architectures to support this Kernel System with the object of implementing one design in silicon. The work has been divided into the architecture of the processing element, the communications between processing elements, and the implementation of list structured memory: a key element of the Kernel System. Besides presenting this VLSI work, relevant material from the Kernel System is presented to provide the context within which the work is taking place.

关键词： parallel computer architecture List-structured memory

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A MULTIPROCESSOR architecture FOR TWO-DIMENSIONAL DIGITAL-FILTERS

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IEEE TRANSACTIONS ON computerS 1987年第7期36卷 876-884页

作者： KIM, JH ALEXANDER, WE N CAROLINA STATE UNIV DEPT ELECT & COMP ENGNRALEIGHNC 27695

In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme, a simple interconnection network, a very high efficiency, and low data transfers and storage requirements. Thus, it avoids the bottlenecks associated with traditional parallel computers and multiprocessor systems.

关键词： Digital signal processing chip fast algorithm image processing multiprocessor system parallel computer architecture two-dimensional filters

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Systolic opportunities for multidimensional data streams

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2002年第4期13卷 388-398页

作者： Chai, SM Wills, DS Motorola Inc Multimedia Architecture Lab Schaumburg IL 60196 USA Georgia Inst Technol Microelect Res Ctr Atlanta GA 30332 USA

Portable image processing applications require an efficient, scalable platform with localized computing regions. This paper presents a new class of area I/O systolic architecture to exploit the physical data locality of planar data streams by processing data where it falls. A synthesis technique using dependence graphs, data partitioning, and computation mapping is developed to handle planar data streams and to systematically design arrays with area I/O. Simulation results show that the use of area I/O provides a 16 times speedup over systems with perimeter I/O. Performance comparisons for a set of signal processing algorithms show that systolic arrays that consider planar data streams in the design process are up to three times faster than traditional arrays.

关键词： parallel computer architecture systolic arrays area I/O design and performance evaluation

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Architectural support for efficient multicasting in irregular networks

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2001年第5期12卷 489-513页

作者： Sivaram, R Kesavan, R Panda, DK Stunkel, CB IBM Corp Enterprise Syst Grp Poughkeepsie NY 12601 USA Network Appliance Sunnyvale CA 94089 USA Ohio State Univ Dept Comp & Informat Sci Columbus OH 43210 USA IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

parallel computing on networks of workstations is fast becoming a cost-effective high-performance computing alternative to MPPs. Such a computing environment typically consists of processing nodes interconnected through a switch-based irregular network. Many of the problems that were solved for regular networks have to be solved anew for these systems. One such problem is that of efficient multicast communication. In this paper, we propose two broad categories of schemes for efficient multicasting in such irregular networks: network interface-based (NI-based) and switch-based. The NI-based multicasting schemes use the network interface of intermediate destinations for absorbing and retransmitting messages to other destinations in the multicast tree. In contrast, the switch-based multicasting schemes use hardware support for packet replication at the switches of the network and a concept known as multidestination routing to convey a multicast message from one source to multiple destinations. We first present alternative schemes for efficient multipacket forwarding at the NI and derive an optimal k-binomial multicast tree for multipacket NI-based multicast. We then propose two switch-based multicasting schemes that differ in the power of the encoding scheme and the complexity of the decoding logic at the switches. These multicasting schemes use path-based multidestination worms that can cover all nodes connected to switches along a valid unicast path and tree-based multidestination worms that can cover entire destination sets in a single phase using one worm, respectively. For each scheme, we describe the associated header encoding and decoding operation, the method for deriving multidestination worms that cover arbitrary multicast destination sets, and the multicasting scheme using the derived multidestination worms. We then compare the NI-based multicasting scheme to the switch-based multicasting schemes with path-based and tree-based multidestination worms using si

关键词： parallel computer architecture cut-through routing multicast broadcast collective communication switch-based networks irregular networks performance evaluation

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Resiliency in numerical algorithm design for extreme scale simulations

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2022年第2期36卷 251-285页

作者： Agullo, Emmanuel Altenbernd, Mirco Anzt, Hartwig Bautista-Gomez, Leonardo Benacchio, Tommaso Bonaventura, Luca Bungartz, Hans-Joachim Chatterjee, Sanjay Ciorba, Florina M. DeBardeleben, Nathan Drzisga, Daniel Eibl, Sebastian Engelmann, Christian Gansterer, Wilfried N. Giraud, Luc Goddeke, Dominik Heisig, Marco Jezequel, Fabienne Kohl, Nils Li, Xiaoye Sherry Lion, Romain Mehl, Miriam Mycek, Paul Obersteiner, Michael Quintana-Orti, Enrique S. Rizzi, Francesco Ruede, Ulrich Schulz, Martin Fung, Fred Speck, Robert Stals, Linda Teranishi, Keita Thibault, Samuel Thoennes, Dominik Wagner, Andreas Wohlmuth, Barbara INRIA Sophia Antipolis France Univ Stuttgart Stuttgart Germany KIT Karlsruher Inst Technol Karlsruhe Germany Barcelona Supercomp Ctr Barcelona Spain Politecn Milan Milan Italy Tech Univ Munich Munich Germany NVIDIA Corp Santa Clara CA USA Univ Basel Basel Switzerland Los Alamos Natl Lab Los Alamos NM USA Univ Erlangen Nurnberg Nurnberg Germany Oak Ridge Natl Lab Oak Ridge TN USA Univ Vienna Vienna Austria Univ Paris 2 Paris France Lawrence Berkeley Natl Lab Berkeley CA USA Univ Bordeaux Bordeaux France CERFACS Toulouse France Univ Politecn Valencia Valencia Spain NexGen Analyt Sheridan WY USA Australian Natl Univ Canberra ACT Australia Forschungszentrum Julich Julich Germany Sandia Natl Labs Livermore CA 94550 USA

This work is based on the seminar titled 'Resiliency in Numerical Algorithm Design for Extreme Scale Simulations' held March 1-6, 2020, at Schloss Dagstuhl, that was attended by all the authors. Advanced supercomputing is characterized by very high computation speeds at the cost of involving an enormous amount of resources and costs. A typical large-scale computation running for 48 h on a system consuming 20 MW, as predicted for exascale systems, would consume a million kWh, corresponding to about 100k Euro in energy cost for executing 10(23) floating-point operations. It is clearly unacceptable to lose the whole computation if any of the several million parallel processes fails during the execution. Moreover, if a single operation suffers from a bit-flip error, should the whole computation be declared invalid? What about the notion of reproducibility itself: should this core paradigm of science be revised and refined for results that are obtained by large-scale simulation? Naive versions of conventional resilience techniques will not scale to the exascale regime: with a main memory footprint of tens of Petabytes, synchronously writing checkpoint data all the way to background storage at frequent intervals will create intolerable overheads in runtime and energy consumption. Forecasts show that the mean time between failures could be lower than the time to recover from such a checkpoint, so that large calculations at scale might not make any progress if robust alternatives are not investigated. More advanced resilience techniques must be devised. The key may lie in exploiting both advanced system features as well as specific application knowledge. Research will face two essential questions: (1) what are the reliability requirements for a particular computation and (2) how do we best design the algorithms and software to meet these requirements? While the analysis of use cases can help understand the particular reliability requirements, the construction of remedies is

关键词： Numerical algorithms parallel computer architecture fault tolerance resilience

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THE IBM BLUE GENE/Q INTERCONNECTION FABRIC

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IEEE MICRO 2012年第1期32卷 32-43页

作者： Chen, Dong Eisley, Noel A. Heidelberger, Philip Senger, Robert M. Sugawara, Yutaka Kumar, Sameer Salapura, Valentina Satterfield, David L. Steinmacher-Burow, Burkhard Parker, Jeffrey J. IBM TJ Watson Res Ctr Blue Gene Supercomp Project Hardware Team Yorktown Hts NY 10598 USA IBM Syst & Technol Grp Rochester MN USA IBM TJ Watson Res Ctr Serv Innovat Lab Yorktown Hts NY 10598 USA

This article describes the ibm blue gene/q interconnection network and message unit. Blue gene/q is the third generation in the ibm blue gene line of massively parallel supercomputers and can be scaled to 20 petaflops and beyond. For better application scalability and performance, blue gene/q has new routing algorithms and techniques to parallelize the injection and reception of packets in the network interface.

关键词： BG/Q Blue Gene/Q Decision support systems interconnect technologies interconnection network message unit network interface architecture parallel computer architecture router architecture routing algorithms and techniques

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UWGSP8: A programmable ultrasound subsystem for native image processing

UWGSP8: A programmable ultrasound subsystem for native image...

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Conference on Image Display

作者： Basoglu, C Reeve, J Kim, YM Marquis, S UNIV WASHINGTON DEPT ELECT ENGNIMAGE COMP SYST LABSEATTLEWA 98195

ISBN: (纸本)0819420824

Tremendous computational capabilities are required in modern ultrasound machines. Unique and very high data throughput rates combined with the demanding processing requirement have restricted the designs of such ultrasound machines to algorithm-specific hardware with limited programmability. Specialized electronic boards are dedicated to each of the several subsystems such as gray scale, color flow, and Doppler processing. In many cases, improving the functionality of an ultrasound machine requires hardware redesigns and replacements of boards or of the entire machine. These redesigns and replacements generally require significant expenditures in manpower, time, and cost, thus imposing stringent limits on the types of image processing which can be supported. In an effort to address these problems, we have architected and designed a high-performance programmable ultrasound processing subsystem, the UWGSP8, to fit within an existing ultrasound machine and support native ultrasound image processing. Its flexible design means that it can support a much wider range of ultrasound image processing algorithms than can be realized in any conventional fixed hardware design.

关键词： ultrasound machines medical imaging native processing signal and image processing ultrasound hardware and software parallel computer architecture

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Proto-cluster: A Multi-device Approach to parallel Computing 17

Proto-cluster: A Multi-device Approach to Parallel Computing

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17th IEEE World Symposium on Applied Machine Intelligence and Informatics (SAMI)

作者： Adam, Norbert Gergely, Tobias Hulic, Michal Hurtuk, Jan Mados, Branislav Tech Univ Kosice Fac Elect Engn & Informat Dept Comp & Informat Kosice Slovakia

ISBN: (纸本)9781728102504

parallel computer architectures play a significant role in the world of informatics. parallel architectures offer the one great opportunity, they offer higher computing performance than serial computers. However, higher computing performance charges higher hardware and software cost. In this publication we are looking for answers for hardware design where the price of the used assembly is low, and the performance is, on the level of robust parallel system, able to solve problems that can be calculated effectively. Our solution is presented as multi-platform architecture with different types of prototyping board connected together that create one independent parallel architecture solving one problem together.

关键词： Arduino cluster decomposition IDE parallel computer architecture Proto-cluster prototyping

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OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator 24

OuterSPACE: An Outer Product based Sparse Matrix Multiplicat...

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24th IEEE International Symposium on High Performance computer architecture (HPCA)

作者： Pal, Subhankar Beaumont, Jonathan Park, Dong-Hyeon Amarnath, Aporva Feng, Siying Chakrabarti, Chaitali Kim, Hun-Seok Blaauw, David Mudge, Trevor Dreslinski, Ronald Univ Michigan Ann Arbor MI 48109 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781538636596

Sparse matrices are widely used in graph and data analytics, machine learning, engineering and scientific applications. This paper describes and analyzes OuterSPACE, an accelerator targeted at applications that involve large sparse matrices. OuterSPACE is a highly-scalable, energy-efficient, reconfigurable design, consisting of massively parallel Single Program, Multiple Data (SPMD)style processing units, distributed memories, high-speed crossbars and High Bandwidth Memory (HBM). We identify redundant memory accesses to non-zeros as a key bottleneck in traditional sparse matrix-matrix multiplication algorithms. To ameliorate this, we implement an outer product based matrix multiplication technique that eliminates redundant accesses by decoupling multiplication from accumulation. We demonstrate that traditional architectures, due to limitations in their memory hierarchies and ability to harness parallelism in the algorithm, are unable to take advantage of this reduction without incurring significant overheads. OuterSPACE is designed to specifically overcome these challenges. We simulate the key components of our architecture using gem5 on a diverse set of matrices from the University of Florida's SuiteSparse collection and the Stanford Network Analysis Project and show a mean speedup of 7.9x over Intel Math Kernel Library on a Xeon CPU, 13.0x against cuSPARSE and 14.0x against CUSP when run on an NVIDIA K40 GPU, while achieving an average throughput of 2.9 GFLOPS within a 24 W power budget in an area of 87 mm2.

关键词： Sparse matrix processing application-specific hardware parallel computer architecture hardware-software codesign hardware accelerators

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Performance and Power Analysis of High-Density Multi-GPGPU architectures: A Preliminary Case Study 17

Performance and Power Analysis of High-Density Multi-GPGPU A...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Gao, Yuxiang Iqbal, Saeed Zhang, Peng Qiu, Meikang Dell Inc Global Solut Engn Grp Round Rock TX 78682 USA SUNY Stony Brook Dept Biomed Engn Stony Brook NY 11794 USA Pace Univ Dept Comp Sci New York NY 10038 USA

ISBN: (纸本)9781479989379

A system architecture with high-density general purpose graphic processing unit (GPGPU) is emerging as a promising solution that can offer high compute performance and performance-per-watt for building cluster supercomputers. The raw compute power of these heterogeneous systems greatly exceeds the current prevailing homogenous systems, motivating their rapid adoption. These heterogeneous systems do however increase the complexity of developing parallel applications and there is a need to investigate the compute performances and associated power consumption of common benchmarks and scientific computing applications. In this paper, we present the performance and power studies through using the Dell C4130 server that integrates up to 4 GPGPU cards and NVIDIA GPGPU K80 is used. The high performance Linpack (HPL) and molecular dynamics (MD) simulators including NAMD, LAMMPS and GROMACS are tested. Through comparing 4-K80 and 2-Xeon E5-2690 v3 systems, we show that: (1) for HPL tests, the 4-GPU server delivers up to 7 TFLOPS that is 9 times faster than the 2-CPU system and its power efficiency is 4 GFLOPS per Watt;(2) for MD tests, NAMD on 4-GPU server achieves 7.8 times speedup and it uses 2.3 times power consumption compared to 2-CPU system;and LAMMPS achieves 16 times speedup and it uses 2.6 times power consumption;and GROMACS achieves 3.3 times speed up and it uses 2.6 times power consumption. These preliminary results demonstrated that the novel high-density multi-GPGPU architecture offers high performances for computing intensive applications and molecular simulators with superior power efficiencies in a space efficient design. In future, such heterogeneous architecture could be a powerful alternative solution for next generation supercomputer systems.

关键词： dense GPGPU architecture parallel computer architecture performance evaluations GPGPU power consumption

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