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CIE International Conference on Radar

作者： Wang, ZB Tang, J Wang, XT Peng, YN Tsing Hua Univ Beijing 100084 Peoples R China

ISBN: (纸本)0780370007

Conventional radar signal processing systems have very limited flexibility because they are designed for their specific applications. For this problem, a general-purpose high-speed radar signal processing system based on parallel computer architecture may be a hopeful solution. One of the key components in such a system is the Processing Node, which is chiefly responsible for the computation-intensive tasks. This paper presents a scheme of the Processing Node using a new multi-DSP parallel computing architecture as the hardware core. This architecture consists of five ADSP-2106x chips. It has many promising characteristics such as strong computational capability, broad I/O bandwidth, various communication methods, topology flexibility, and good expansion capability.

关键词： radar signal processing digital signal processing chips parallel architectures radar computing high-speed system parallel computer architecture processing node multi-DSP architecture parallel computing hardware core ADSP-2106x chips radar signal processing

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Interdisciplinary Design of a Research Experience on Microelectronic Systems for K-12 Students

Interdisciplinary Design of a Research Experience on Microel...

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10th European Workshop on Microelectronics Education (EWME)

作者： Mazzoni, Valentina Bertozzi, Davide Univ Verona Dept Philosophy Educ & Psychol I-37100 Verona Italy Univ Ferrara Dept Engn Ferrara Italy

ISBN: (纸本)9781479940165

The approach to microelectronics education is typically geared towards the knowledge of the principles behind electronic circuits and systems, but there are social indicators that it overlooks some important educative aspects such as thinking competences and social attitudes. Such aspects play a fundamental role when bringing microelectronics education to the K-12 level. Therefore, the need to couple the acquisition of technical skills and concepts with a truly educative experience arises. In order to tackle this challenge, we propose to bring the research experience in electrical engineering within reach of K-12 students, because the active knowledge construction process that takes place during research requires children to be engaged with all of their knowledge, skills and attitudes. This poses the challenge of overcoming the knowledge gap of students, which we address by means of a synergistic cooperation of electronic experts and educators. More specifically, we propose the narrative approach as a key enabler for participatory research with K-12 students under the guidance of an expert.

关键词： participatory research k-12 students narrative approach problem-oriented project work parallel computer architecture networks-on-chip

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A Dynamically Configurable Coprocessor for Convolutional Neural Networks 10

A Dynamically Configurable Coprocessor for Convolutional Neu...

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37th International Symposium on computer architecture

作者： Chakradhar, Srimat Sankaradas, Murugan Jakkula, Venkata Cadambi, Srihari NEC Labs Amer Inc Princeton NJ 08540 USA

ISBN: (纸本)9781450300520

Convolutional neural networks (CNN) applications range from recognition and reasoning (such as handwriting recognition, facial expression recognition and video surveillance) to intelligent text applications such as semantic text analysis and natural language processing applications. Two key observations drive the design of a new architecture for CNN. First, CNN workloads exhibit a widely varying mix of three types of parallelism: parallelism within a convolution operation, intra-output parallelism where multiple input sources (features) are combined to create a single output, and inter-output parallelism where multiple, independent outputs (features) are computed simultaneously. Workloads differ significantly across different CNN applications, and across different layers of a CNN. Second, the number of processing elements in an architecture continues to scale (as per Moore's law) much faster than off-chip memory bandwidth (or pin-count) of chips. Based on these two observations, we show that for a given number of processing elements and off-chip memory bandwidth, a new CNN hardware architecture that dynamically configures the hardware on-the-fly to match the specific mix of parallelism in a given workload gives the best throughput performance. Our CNN compiler automatically translates high abstraction network specification into a parallel microprogram (a sequence of low-level VLIW instructions) that is mapped, scheduled and executed by the coprocessor. Compared to a 2.3 GHz quad-core, dual socket Intel Xeon, 1.35 GHz C870 GPU, and a 200 MHz FPGA implementation, our 120 MHz dynamically configurable architecture is 4x to 8x faster. This is the first CNN architecture to achieve real-time video stream processing (25 to 30 frames per second) on a wide range of object detection and recognition tasks.

关键词： Convolutional Neural Networks Dynamic Reconfiguration parallel computer architecture

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SymSig: A Low Latency interconnection topology for HPC clusters

SymSig: A Low Latency interconnection topology for HPC clust...

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20th International Conference on High Performance Computing (HiPC)

作者： Brahme, Dhananjay Bhardwaj, Onkar Chaudhary, Vipin Tata Consultancy Serv Ctr Excellence High Performance Comp Pune 411057 Maharashtra India Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA SUNY Buffalo Dept Comp Sci & Engn Buffalo NY 14260 USA

ISBN: (纸本)9781479907298

This paper presents the underlying theory and the performance of a cluster using a new 2-hop network topology. This topology is constructed using a symmetric equation and Singer Difference Sets and is called SymSig. The degree of connections at each node with SymSig is about half compared to previous methods using Singer Difference Sets. A comparison with a cluster of Clos topology shows significant advantages. The worst case congestion in SymSig topology for unicast permutation is 2, where as in Clos it is proportional to the radix of the building block switches used. The number of switches required is smaller by about 25%, the size of the cluster is larger by about 15% and the worst bandwidth is better by about 50% for SymSig. These advantages are retained for peta and exascale systems. Its performance on a set of collectives like exchange-all, shift-all, broadcast-all and all-to-all send/receive shows improvements ranging from 39% to 83%. Its performance on a molecular dynamics application GROMMACS shows improvement of upto 33%. This network is particularly suitable for applications that require global all to all communications. The low latency of this network makes it scaleable and an attractive alternative for building peta and exascale systems.

关键词： network topology bandwidth latency computer architecture parallel computing parallel computer architecture high performance computing exascale computing benchmark communication library functions high performance computing applications routing algorithms and techniques

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A system for evaluating performance and cost of SIMD array designs 7

A system for evaluating performance and cost of SIMD array d...

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7th Symposium on the Frontiers of Massively parallel Computation (Frontiers 99)

作者： Herbordt, MC Cravy, J Sam, R Kidwai, O Lin, C Univ Houston Dept Elect & Comp Engn Houston TX 77204 USA

ISBN: (纸本)0769500870

SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The method we use is to bridge the gap between architecture-level and EDA-level modeling by using an EDA-based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture-level simulator but also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. We have used our system to evaluate hundreds of potential SIMD array designs with respect to real applications. Some of the results were surprising: the slowdown caused by underutilized resources was significantly more than we had anticipated.

关键词： SIMD computers parallel computer architecture computer design evaluation computer simulation domain specific systems

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Efficient, scalable, and fair read-modify-writes

Efficient, scalable, and fair read-modify-writes

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作者： Rajaram, Bharghava University of Edinburgh

学位级别：doctor

Read-Modify-Write (RMW) operations, or atomics, have widespread application in (a) synchronization, where they are used as building blocks of various synchronization constructs like locks, barriers, and lock-free data structures (b) supervised memory systems, where every memory operation is effectively an RMW that reads and modifies metadata associated with memory addresses and (c) profiling, where RMW instructions are used to increment shared counters to convey meaningful statistics about a program. In each of these scenarios, the RMWs pose a bottleneck to performance and scalability. We observed that the cost of RMWs is dependent on two major factors – the memory ordering enforced by the RMW, and contention amongst processors performing RMWs to the same memory address. In the case of both synchronization and supervised memory systems, the RMWs are expensive due to the memory ordering enforced due to the atomic RMW operation. Performance overhead due to contention is more prevalent in parallel programs which frequently make use of RMWs to update concurrent data structures in a non-blocking manner. Such programs also suffer from a degradation in fairness amongst concurrent processors. In this thesis, we study the cost of RMWs in the above applications, and present solutions to obtain better performance and scalability from RMW operations. Firstly, this thesis tackles the large overhead of RMW instructions when used for synchronization in the widely used x86 processor architectures, like in Intel, AMD, and Sun processors. The x86 processor architecture implements a variation of the Total-Store-Order (TSO) memory consistency model. RMW instructions in existing TSO architectures (we call them type-1 RMW) are ordered like memory fences, which makes them expensive. The strong fence-like ordering of type-1 RMWs is unnecessary for the memory ordering required by synchronization. We propose weaker RMW instructions for TSO consistency; we consider two weaker definitions: typ

关键词： parallel computer architecture atomic instructions efficient synchronization

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The Implementation of Ray Tracing Algorithm with OpenMP parallelization

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Journal of computer and Communications 2024年第1期12卷 120-130页

作者： Noor Alnasser Raghad Alabssi Batool Faran Latifah Alessa Naya Nagy College of Computer Science and IT Imam Abdulrahman Bin Faisal University Dammam Kingdom of Saudi Arabia

Ray tracing is a computer graphics method that renders images realistically. As the name suggests, this technique primarily traces the path of light rays interacting with objects in a scene [1], permitting the calculation of lighting and reflecting impact [2]. As ray tracing is a time-consuming process, the need for parallelization to solve this problem arises. One downside of this solution is the existence of race conditions. In this work, we explore and experiment with a different, well-known solution for this race condition. Starting with the introduction and the background section, a brief overview of the topic is followed by a detailed part of how the race conditions may occur in the case of the ray tracing algorithm. Continuing with the methods and results section, we have used OpenMP to parallelize the Ray tracing algorithm with the different compiler directives critical, atomic, and first-private. Hence, it concluded that both critical and atomic are not efficient solutions to produce a good-quality picture, but first-private succeeded in producing a high-quality picture.

关键词： parallelization Ray Tracing parallel computer architecture OpenMP

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EMBEDDING A COMPLETE BINARY TREE INTO A THREE-DIMENSIONAL GRID

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Journal of Interconnection Networks 2004年第2期5卷 111-130页

作者： WOLFGANG W. BEIN LAWRENCE L. LARMORE CHARLES O. SHIELDS, JR. I. HAL SUDBOROUGH School of Computer Science University of Nevada Las Vegas NV 89154 USA Department of Computer Science University of Texas at Dallas Richardson TX 75083 USA

We describe total congestion 1 embeddings of complete binary trees into three dimensional grids with low expansion ratio r. That is, we give a one-to-one embedding of any complete binary tree into a hexahedron shaped grid such that (a) the number of nodes in the grid is at most r times the number of nodes in the tree, and (b) no tree nodes or edges occupy the same grid positions. The first strategy embeds trees into cube shaped 3D grids. That is, 3D grids in which all dimensions are roughly equal in size, and which thus have no limit in the number of layers. The technique uses a recursive scheme, and we obtain an expansion ratio of r=1.09375. We then give strategies which embed trees into flat 3D grid shapes. That is, we map complete binary trees into 3D grids with a fixed, small number of layers k. Using again a recursive scheme, for k=2, we obtain r=1.25. By a rather different technique, which intricately weaves the branches of various subtrees into each other, we are able to obtain very tight embeddings: We have r=1.171875 for embeddings into five layer grids and r=1.09375 for embeddings into seven layer grids.

关键词： VLSI Layout parallel computer architecture Tree Embeddings Three-Dimensional Grids Expansion Ratio

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AN OPTICALLY INTERCONNECTED DISTRIBUTED SHARED MEMORY SYSTEM: architecture AND PERFORMANCE ANALYSIS

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International Journal of High Speed Computing 1992年第3期4卷 179-212页

作者： KALYANI BOGINENI PATRICK W. DOWD Department of Electrical and Computer Engineering State University of New York at Buffalo Buffalo NY 14260 USA

This paper introduces an optically interconnected distributed shared memory system. The distributed shared memory approach integrates both shared memory and distributed memory system ideas to extract the strengths of each while balancing their respective weaknesses. The system is a system based on a photonic network to support the high communication requirement of . The employs wavelength division multiple access on the photonic network, enabling multiple channels to be formed on a single optical fiber. A result of the high communication capacity is the simplification of the global address mapping problem. This simplified uniform address allocation scheme is introduced. The advantages of the proposed approach are examined through a performance analysis based on a closed queueing network which has been validated through extensive simulation. The performance of the system is evaluated in terms of transaction time of a memory request and system throughput. The impact of variations in the number of channels and processors in the system on these metrics is studied. The effect of variations in memory and channel service times are also evaluated.

关键词： parallel computer architecture distributed shared memory optical communication wavelength division multiplexing performance analysis

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Perspective of parallel Simulation in Mechatronic Systems – Metal Cutting

Perspective of Parallel Simulation in Mechatronic Systems –...

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2013 International Conference on MEMS and Mechanics(MEMSM 2013)

作者： Rozmarína Dubovská Peter Kvasnica Igor Kvasnica University of Hradec Kralove

ISBN: (纸本)9781627489256

The method of simulation design at the computer systems is discussed. In the system identification theory of systems, modelling a program implementation is presented. The simulation of systems depends on definition of their mathematical models. The simulation method is rooted in the fact it is an experimental method comprising aspect like model calibration and data collection. These models are presented in a matrix form in a very good way. A matrix form is often employed to define tasks in the field of science and engineering.. The result of simulation of mathematical models of mechatronic devices, control and communication technology, control, climate changes and etc. can be created using parallel computer architecture. Advantages for users are presented by practical example of cutting process associated with the simulation of the observer.

关键词： model system simulation mathematical models parallel computer architecture

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