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10th International Conference on Swarm Intelligence (ICSI)

作者： Larkin, Eugene, V Antonov, Maxim A. Tula State Univ Tula 300012 Russia

ISBN: (纸本)9783030263539;9783030263546

The necessity of converting a serial interface into a parallel interface, when entering data into the Von-Neumann computer, as a result of the poling procedure, is shown. An algorithm for the operation of the interface converter has been proposed, and it has been shown that the use of serial interface conversion of multiple sensors into a parallel interface, with the ability to access each sensor separately, has greater speed than accessing each sensor separately through a serial interface. The possible technical implementation of the proposed algorithm on the FPGA is shown.

关键词： Serial interface parallel interface Algorithm Time delays Gyroscope Mobile robot FPGA

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Apple :: Lisa :: Brochures :: parallel interface Brochure Jan83

引用

2016年

Apple :: Lisa :: Brochures :: parallel interface Brochure Jan83 by published by

关键词： apple board brochure brochures bytes canada interface interface board jan83 parallel parallel interface programmable terface tlx versatile

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Apple :: Lisa :: Service :: 029-0176-A Lisa parallel interface Card

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2016年

Apple :: Lisa :: Service :: 029-0176-A Lisa parallel interface Card by published by

关键词： 029-0176-a apple authorized lisa connector data data sheet interface interface card internal connector lisa lisa internal parallel parallel connector parallel interface profile hard schematic service slot software software described technical appendix

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Calcomp :: H-84-0045B Vistagraphic Dr11W Dr11B Dr11C and Dr11B parallel interface Users Manual Nov1984

引用

2016年

Calcomp :: H-84-0045B Vistagraphic Dr11W Dr11B Dr11C and Dr11B parallel interface Users Manual Nov1984 by published by

关键词： assy cables calcomp circuit card dma dr11b dr11c dr11w h-84-0045b host host interface inches tolerances input interconnect panel interface memory address parallel parallel interface parts list register bit spi vistagraphic word count zone ltr

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Sandersassociates :: Graphic7 :: Op-330 Rev H interface Control Document Sel Hsd-9132 Graphic 7 32-Bit parallel interface 23Jan1981

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2016年

Sandersassociates :: Graphic7 :: Op-330 Rev H interface Control Document Sel Hsd-9132 Graphic 7 32-Bit parallel interface 23Jan1981 by published by

关键词： 23jan1981 32-bit code ident control data data ready detects document dwg graphic graphic7 high logic host host detects input input data interface logic logic level low logic output data parallel parallel interface signal size code

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Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin parallel interface

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2010年第1期10卷 45-48页

作者： Lee, Jang-Woo Kim, Hong-Jung Nam, Young-Jin Yoo, Changsik Hanyang Univ Div Elect & Comp Engn Seoul 133791 South Korea

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

关键词： parallel interface inter-pin skew skew compensation CMOS DDR4 SDRAM

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Skew Compensation Technique for Source-Synchronous parallel DRAM interface

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2013年第11期21卷 2155-2159页

作者： Lee, Jang-Woo Kim, Hong-Jung Jeong, Chun-Seok Lee, Jae-Jin Yoo, Changsik Hanyang Univ Integrated Circuits Lab Seoul 133791 South Korea SK Hynix Semicond Inchon 467866 South Korea

The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13-mu m standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin x8 parallel interface.

关键词： CMOS delay-locked loop (DLL) interpin skew compensation parallel interface synchronous DRAM (SDRAM)

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Multi-scale parallel and texture interface to enhance thermoelectric performance of p-type Ca3Co4O9 semiconductor materials

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APPLIED SURFACE SCIENCE 2024年 661卷

作者： Shi, Zongmo Han, Zhen Wei, Jian Chen, Chanli Zhang, Ying Yuan, Hudie Song, Fang Zhang, Junzhan He, Geping Li, Xueting Xian Univ Architecture & Technol Sch Mat Sci & Engn Xian 710055 Peoples R China Xian Univ Architecture & Technol Instrumental Anal Ctr Xian 710055 Peoples R China Shaanxi Key Lab Nano Mat & Technol Xian 710055 Peoples R China

Ca3Co4O9 is considered as an attractive material for high -temperature area application. The correlation between structure modulation and electric -thermal transport properties is an important prerequisite to optimize thermoelectric performance of Ca3Co4O9 materials. p -type Ca3Co4O9 -based ceramics with texture interface were successfully prepared by tape casting method. The different content of template seeds was added into the Ca3Co4O9 semiconductor, successfully constructing the parallel interfaces. The "brick -wall" structure was formed due to the liquid film existed at grain boundaries. The sample with 15 wt% template seeds additives yielded similar to 60 % rise in power factor with a peak value of 0.33 mW/(m center dot K-2), and the low thermal conductivity of 0.97 W/(m center dot K) was obtained at 800 degrees C. Additionally, the ZT value reached 0.34 due to the presence of multi -scale parallel interfaces among the stripe -like grains, which effectively scattered the long -wave, middle -wave and short-wave phonons and strengthened the charge carrier transporting. This texturing method offered a meaningful way for enhancing thermoelectric properties of oxides thermoelectric materials.

关键词： Texturing parallel interface Thermoelectric properties Ca3Co4O9

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Interfacing FPGA with high-speed data converter using parallel and serial interface

Interfacing FPGA with high-speed data converter using parall...

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2017中国电子设计创新大会

作者： Marc Stackler Andrew Glascott-Jones Romain Pilard Nicolas Chantier e2v semiconductors division ＃309 Building1Coastal business centerXinghua RoadShekouNanshan Distr e2v semiconductors division

The current trend for many application requiring data converters is to get closer and closer to a full SDR(Software Defined Radio)*** SDR architecture brings many benefits in terms of flexibility and SWaP-C(Size,Weight,Power and Cost)it often translates into higher bandwidth capability and is directly linked to the data converter sampling speed with the Shannon-Nyquist *** this complicates the interface between FPGA(Field Programmable Gate Array)and data *** the speed at which FPGA process information is very limited compared to the amount of data generated by high-speed data *** course,this is dealt through massive parallel *** transmitting and receiving this huge amount of data has become the system bottleneck as data needs to be transmitted in larger and larger quantities,faster and *** paper covers and compares the two means of interfacing at high-speed between FPGA and data converter currently used today: high-speed LVDS parallel interface and high-speed serial *** considers multiple aspects ranging from RF with trace length and signal integrity to the system level with cost and ease of *** starts by introducing these 2 types of interfaces,comparing them and identifying their benefits and *** it discusses the FPGA design of a high-speed parallel interface at *** focuses on a transmission from an FPGA to a DAC(Digital to Analog Converter)using the example of an Arria V FPGA from Altera interfacing with an EV12DS460A from *** concluding,it covers a high-speed serial interface FPGA design at 6Gbps using the ESIstream(Efficient Serial interface)*** focuses on a transmission from an ADC(Analog to Digital Converter)to an FPGA using the example of an EV12AD500A from e2v interfacing with a Virtex 7 from Xilinx.

关键词： ADC DAC FPGA EV12AD500 EV12DS460 Arria V Virtex 7 ESIstream serial interface parallel interface

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Dynamics Modeling for parallel Haptic interfaces with Force Sensing and Control

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IEEE TRANSACTIONS ON HAPTICS 2013年第4期6卷 429-439页

作者： Bernstein, Nicholas Lawrence, Dale Pao, Lucy Intuit Surg Inc Sunnyvale CA 94086 USA Univ Colorado Boulder CO 80309 USA

Closed-loop force control can be used on haptic interfaces (HIs) to mitigate the effects of mechanism dynamics. A single multidimensional force-torque sensor is often employed to measure the interaction force between the haptic device and the user's hand. The parallel haptic interface at the University of Colorado (CU) instead employs smaller 1D force sensors oriented along each of the five actuating rods to build up a 5D force vector. This paper shows that a particular manipulandum/hand partition in the system dynamics is induced by the placement and type of force sensing, and discusses the implications on force and impedance control for parallel haptic interfaces. The details of a "squaring down" process are also discussed, showing how to obtain reduced degree-of-freedom models from the general six degree-of-freedom dynamics formulation.

关键词： parallel interface dynamics modeling force control perceived impedance force sensing squaring down

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