咨询与建议

限定检索结果

文献类型

  • 8 篇 期刊文献
  • 6 篇 会议

馆藏范围

  • 14 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 12 篇 工学
    • 7 篇 电子科学与技术(可...
    • 7 篇 计算机科学与技术...
    • 5 篇 电气工程
    • 1 篇 软件工程

主题

  • 14 篇 parallel logic s...
  • 3 篇 multilevel parti...
  • 3 篇 f-m heuristic al...
  • 3 篇 synchronous simu...
  • 3 篇 synchronization
  • 3 篇 discovery
  • 2 篇 event-driven sim...
  • 2 篇 load balancing
  • 2 篇 time warp
  • 2 篇 distributed simu...
  • 2 篇 concurrency
  • 1 篇 many integrated ...
  • 1 篇 spmd
  • 1 篇 asynchronous sim...
  • 1 篇 graphics process...
  • 1 篇 simulation
  • 1 篇 vector multiproc...
  • 1 篇 gpgpu
  • 1 篇 gate level logic...
  • 1 篇 discrete event s...

机构

  • 2 篇 school of comput...
  • 1 篇 shantou univ key...
  • 1 篇 state university...
  • 1 篇 bogazici univ de...
  • 1 篇 wright state uni...
  • 1 篇 microsoft
  • 1 篇 computer science...
  • 1 篇 school of microe...
  • 1 篇 university of ma...
  • 1 篇 mentor wilsonvil...
  • 1 篇 state university...
  • 1 篇 nara natl coll o...
  • 1 篇 university of br...
  • 1 篇 schoold of micro...
  • 1 篇 lg semicon co lt...
  • 1 篇 univ glasgow sch...
  • 1 篇 suny stony brook...
  • 1 篇 washington univ ...
  • 1 篇 school of comput...
  • 1 篇 washington state...

作者

  • 2 篇 mahmood a
  • 2 篇 baker wi
  • 1 篇 yuzhuo fu
  • 1 篇 kormicki maciek
  • 1 篇 wang jiafang
  • 1 篇 aksanli baris
  • 1 篇 kim hk
  • 1 篇 kikuno t
  • 1 篇 jiafang wang
  • 1 篇 jiafang wang sch...
  • 1 篇 fu yuzhuo
  • 1 篇 tsai hans
  • 1 篇 jean j
  • 1 篇 gu pei
  • 1 篇 zhang qiting
  • 1 篇 seko t
  • 1 篇 lai liyang
  • 1 篇 hong k. kim
  • 1 篇 cockshott paul
  • 1 篇 mahmood ausif

语言

  • 10 篇 英文
  • 4 篇 其他
检索条件"主题词=Parallel Logic Simulation"
14 条 记 录,以下是11-20 订阅
排序:
Concurrency preserving partitioning (CPP) for parallel logic simulation  96
Concurrency preserving partitioning (CPP) for parallel logic...
收藏 引用
Proceedings of the tenth workshop on parallel and distributed simulation
作者: Hong K. Kim Jack Jean Department of Computer Science and Engineering Wright State University Dayton Ohio
Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves ... 详细信息
来源: 评论
parallel event-driven logic simulation algorithms: Tutorial and comparative evaluation
收藏 引用
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1996年 第4期143卷 177-185页
作者: Baker, WI Mahmood, A Carlson, BS UNIV BRIDGEPORT BRIDGEPORTCT 06601 SUNY STONY BROOK STONY BROOKNY 11794
parallel processing offers a viable way to improve the enormous execution time of the simulation of large VLSI designs. Various parallel logic simulation approaches have been proposed in recent years resulting in some... 详细信息
来源: 评论
EXPERIMENTAL EVALUATION OF DYNAMIC SCHEDULING FOR parallel logic simulation USING BENCHMARK CIRCUITS
收藏 引用
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年 第11期E77A卷 1910-1912页
作者: SEKO, T KIKUNO, T Nara Natl Coll of Technology Yamatokoriyama-shi Japan
We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time-first method, the ... 详细信息
来源: 评论
An evaluation of parallel synchronous and conservative asynchronous logic-level simulations
收藏 引用
VLSI DESIGN 1996年 第2期4卷 91-105页
作者: Mahmood, A Baker, WI WASHINGTON UNIV TRI CITIES RICHLANDWA 99352
A recent paper by Bailey [1] contains a theorem stating that the idealized execution times of unit-delay, synchronous and conservative asynchronous simulations are equal under the conditions that unlimited number of p... 详细信息
来源: 评论