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29th Euromicro International Conference on parallel, Distributed and Network-Based Processing (PDP)

作者： Vogel, Adriano Mencagli, Gabriele Griebler, Dalvan Danelutto, Marco Fernandes, Luiz Gustavo Pontifical Catholic Univ Rio Grande do Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres de Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Univ Pisa UNIPI Comp Sci Dept Pisa Italy

ISBN: (纸本)9781665414555

Stream processing applications compute streams of data and provide insightful results in a timely manner, where parallel computing is necessary for accelerating the application executions. Considering that these applications are becoming increasingly dynamic and lung-running, a potential solution is to apply dynamic runtime changes. However, it is challenging for humans to continuously monitor and manually self-optimize the executions. In this paper, we propose self-adaptiveness of the parallel patterns used, enabling flexible on-the-fly adaptations. The proposed solution is evaluated with an existing programming framework and running experiments with a synthetic and a real-world application. The results show that the proposed solution is able to dynamically self-adapt to the most suitable parallel pattern configuration and achieve performance competitive with the best static cases. The feasibility of the proposed solution encourages future optimizations and other applicabilities.

关键词： parallel Computing parallel patterns parallelism Abstractions Self adaptive systems Stream Processing

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Have Abstraction and Eat Performance, Too: Optimized Heterogeneous Computing with parallel patterns 16

Have Abstraction and Eat Performance, Too: Optimized Heterog...

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14th International Symposium on Code Generation and Optimization (CGO)

作者： Brown, Kevin J. Lee, HyoukJoong Rompf, Tiark Sujeeth, Arvind K. De Sa, Christopher Aberger, Christopher Olukotun, Kunle Stanford Univ Stanford CA 94305 USA Purdue Univ W Lafayette IN 47907 USA Google Mountain View CA USA

ISBN: (纸本)9781450337786

High performance in modern computing platforms requires programs to be parallel, distributed, and run on heterogeneous hardware. However programming such architectures is extremely difficult due to the need to implement the application using multiple programming models and combine them together in ad-hoc ways. To optimize distributed applications both for modern hardware and for modern programmers we need a programming model that is sufficiently expressive to support a variety of parallel applications, sufficiently performant to surpass hand-optimized sequential implementations, and sufficiently portable to support a variety of heterogeneous hardware. Unfortunately existing systems tend to fall short of these requirements. In this paper we introduce the Distributed Multiloop Language (DMLL), a new intermediate language based on common parallel patterns that captures the necessary semantic knowledge to efficiently target distributed heterogeneous architectures. We show straightforward analyses that determine what data to distribute based on its usage as well as powerful transformations of nested patterns that restructure computation to enable distribution and optimize for heterogeneous devices. We present experimental results for a range of applications spanning multiple domains and demonstrate highly efficient execution compared to manually-optimized counterparts in multiple distributed programming models.

关键词： parallel patterns distributed memory pattern transformations

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Supporting MPI-distributed stream parallel patterns in GRPPI 18

Supporting MPI-distributed stream parallel patterns in GRPPI

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25th European MPI Users' Group Meeting (EuroMPI)

作者： Fernandez Munoz, Javier Dolz, Manuel F. del Rio Astorga, David Prieto Cepeda, Javier Daniel Garcia, J. Univ Carlos III Madrid Leganes 28911 Spain

ISBN: (纸本)9781450364928

In the recent years, the large volumes of stream data and the near real-time requirements of data streaming applications have exacerbated the need for new scalable algorithms and programming interfaces for distributed and shared-memory platforms. To contribute in this direction, this paper presents a new distributed MPI back end for GrPPI, a C++ high-level generic interface of data-intensive and stream processing parallel patterns. This back end, as a new execution policy, supports the distributed and hybrid (distributed and shared-memory) parallel execution of the Pipeline and Farm patterns, where the hybrid mode combines the MPI policy with a GrPPI shared-memory one. A detailed analysis of the GrPPI MPI execution policy reports considerable benefits from the programmability, flexibility and readability points of view. The experimental evaluation on a streaming application with different distributed and shared-memory scenarios reports considerable performance gains with respect to the sequential versions at the expense of negligible GrPPI overheads.

关键词： parallel patterns Stream Processing Distributed patterns C plus plus Programming Generic Programming

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Towards high-level parallel patterns in OpenCL 15

Towards high-level parallel patterns in OpenCL

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15th International Conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Dokulil, Jiri Benkner, Siegfried Univ Vienna Res Grp Sci Comp A-1010 Vienna Austria

ISBN: (纸本)9781479983346

parallel pattern libraries (e.g., Intel TBB) are popular and useful tools for developing applications in SMP environments at a higher level of abstraction. Such libraries execute user-provided code efficiently on shared memory parallel architectures in accordance with well-defined execution patterns like parallel for-loops or pipelines. For heterogeneous architectures comprised of CPUs and accelerators, OpenCL has gained a lot of momentum. Since accelerated architectures do not provide a shared memory, it is not possible to directly use the approach taken in pattern libraries for SMP systems for OpenCL as well. In this paper, we are exploring issues and opportunities encountered by attempts to provide such patterns in the context of OpenCL. Based on a set of experiments with a scientific application on diverse OpenCL devices, we point out major pitfalls and insights, and outline directions for further efforts in developing pattern libraries for OpenCL.

关键词： OpenCL parallel patterns parallel mode shared memory Libraries switched mode power supplies parallel Lines parallel architectures central processing units level of abstraction ARCHITECTURE pipeline

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Generating Configurable Hardware from parallel patterns 16

Generating Configurable Hardware from Parallel Patterns

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21st International Conference on Architectural Support for Programming Languages and Operating Systems

作者： Prabhakar, Raghu Koeplinger, David Brown, Kevin J. Lee, HyoukJoong De Sa, Christopher Kozyrakis, Christos Olukotun, Kunle Stanford Univ Stanford CA 94305 USA Stanford Univ EPFL Stanford CA 94305 USA

ISBN: (纸本)9781450340915

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4x on a set of benchmarks from the data analytics domain.

关键词： Hardware generation tiling metapipelining parallel patterns reconfigurable hardware FPGAs

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Plasticine: A Reconfigurable Architecture For parallel patterns

Plasticine: A Reconfigurable Architecture For Parallel Patte...

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44th Annual International Symposium on Computer Architecture (ISCA)

作者： Prabhakar, Raghu Zhang, Yaqi Koeplinger, David Feldman, Matt Zhao, Tian Hadjis, Stefan Pedram, Ardavan Kozyrakis, Christos Olukotun, Kunle Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450348928

Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long compilation times. We address both challenges with Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns. parallel patterns have emerged from recent research on parallel programming as powerful, high-level abstractions that can elegantly capture data locality, memory access patterns, and parallelism across a wide range of dense and sparse applications. We motivate Plasticine by first observing key application characteristics captured by parallel patterns that are amenable to hardware acceleration, such as hierarchical parallelism, data locality, memory access patterns, and control flow. Based on these observations, we architect Plasticine as a collection of Pattern Compute Units and Pattern Memory Units. Pattern Compute Units are multi-stage pipelines of reconfigurable SIMD functional units that can efficiently execute nested patterns. Data locality is exploited in Pattern Memory Units using banked scratchpad memories and configurable address decoders. Multiple on-chip address generators and scatter-gather engines make efficient use of DRAM bandwidth by supporting a large number of outstanding memory requests, memory coalescing, and burst mode for dense accesses. Plasticine has an area footprint of 113 mm(2) in a 28nm process, and consumes a maximum power of 49 W at a 1 GHz clock. Using a cycle-accurate simulator, we demonstrate that Plasticine provides an improvement of up to 76.9x in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.

关键词： parallel patterns reconfigurable architectures hardware accelerators CGRAs

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Generating Configurable Hardware from parallel patterns

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ACM SIGPLAN NOTICES 2016年第4期51卷 651-665页

关键词： Hardware generation tiling metapipelining parallel patterns reconfigurable hardware FPGAs

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A Comparative Analysis of the Performance of Scalable parallel patterns Applied to Genetic Algorithms and Configured for NVIDIA GPUs

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Procedia Computer Science 2017年 114卷 65-72页

作者： David Radford David Calvert School of Computer Science University of Guelph Guelph N1G2W1 Canada

parallel programming patterns are built upon a foundation of serial programming patterns to maximize the efficiency of parallel code and effectively use parallel resources available in a given system. This work focuses on using NVIDIA GPUs with the CUDA C library for parallel computing. The goal is to implement parallel versions of a genetic algorithm using the Map and Fork-Join parallel patterns to improve its performance. The intent is to demonstrate that the parallel patterns can be implemented on the CUDA platform and achieve increases in speedup, efficiency, and scalability with the parallel genetic algorithms. A comparative assessment of the two parallel patterns is conducted by configuring them to evaluate instances of the Travelling Salesman Problem (TSP) using different data sets. This assessment considers each algorithm’s run time performance, their use of system resources, and their required overhead.

关键词： parallel patterns Genetic Algorithm parallel Computing Travelling Salesman Problem

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Data stream processing via code annotations

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JOURNAL OF SUPERCOMPUTING 2018年第11期74卷 5659-5673页

作者： Danelutto, Marco De Matteis, Tiziano Mencagli, Gabriele Torquati, Massimo Univ Pisa Dept Comp Sci Pisa Italy

Time-to-solution is an important metric when parallelizing existing code. The REPARA approach provides a systematic way to instantiate stream and data parallel patterns by annotating the sequential source code with attributes. Annotations are automatically transformed in a target parallel code that uses existing libraries for parallel programming (e.g., FastFlow). In this paper, we apply this approach for the parallelization of a data stream processing application. The description shows the effectiveness of the approach in easily and quickly prototyping several parallel variants of the sequential code by obtaining good overall performance in terms of both throughput and latency.

关键词： Code annotations parallel patterns Data stream processing

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parallel pattern-based systems for computational biology: A case study

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2006年第8期17卷 750-763页

作者： Liu, Weiguo Schmidt, Bertil Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

Computational biology research is now faced with the burgeoning number of genome data. The rigorous postprocessing of this data requires an increased role for high-performance computing ( HPC). Because the development of HPC applications for computational biology problems is much more complex than the corresponding sequential applications, existing traditional programming techniques have demonstrated their inadequacy. Many high level programming techniques, such as skeleton and pattern-based programming, have therefore been designed to provide users new ways to get HPC applications without much effort. However, most of them remain absent from the mainstream practice for computational biology. In this paper, we present a new parallel pattern-based system prototype for computational biology. The underlying programming techniques are based on generic programming, a programming technique suited for the generic representation of abstract concepts. This allows the system to be built in a generic way at application level and, thus, provides good extensibility and flexibility. We show how this system can be used to develop HPC applications for popular computational biology algorithms and lead to significant runtime savings on distributed memory architectures.

关键词： high-performance computational biology dynamic programming algorithms hierarchical parallel genetic algorithms parallel patterns generic programming

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