检索结果-内蒙古大学图书馆

An adaptive parallel pipeline pattern for grids

An adaptive parallel pipeline pattern for grids

10th Workshop on Advances in parallel and Distributed Computational Models/22nd IEEE International parallel and Distributed Processing Symposium

作者： Gonzalez-Velez, Horacio Cole, Murray Univ Edinburgh Sch Informat Inst Comp Syst Architecture Edinburgh EH8 9YL Midlothian Scotland Univ Edinburgh Sch Informat Inst Comp Syst Architecture Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781424416936

This paper introduces an adaptive parallel pipeline pattern which follows the GRASP (Grid-Adaptive Structured parallelism) methodology. GRASP is a generic methodology to incorporate structural information at compile time into a parallel program that enables it to adapt automatically to dynamic variations in resource performance. GRASP instruments the pipeline with a series of pragmatic rules, which depend on particular performance thresholds based on the computation/communication patterns of the program and the availability of resources in the grid. Our parallel pipeline pattern is implemented as a parameterisable C/MPI AN using a variable-size input data vector and a stage function array. We have evaluated its efficiency using a numerical benchmark stage function in a non-dedicated computational grid environment.

关键词： algorithmic skeletons parallel patterns parallel programming structured parallelism grid computing grid resource management

来源：评论

学校读者我要写书评

暂无评论

A Pattern-Based Comparison of OpenACC and OpenMP for Accelerator Computing 1

引用

20th European Conference on parallel Computing (Euro-Par)

作者： Wienke, Sandra Terboven, Christian Beyer, James C. Mueller, Matthias S. Rhein Westfal TH Aachen IT Ctr D-52074 Aachen Germany JARA High Performance Comp D-52062 Aachen Germany Cray Inc St Paul MN USA

ISBN: (数字)9783319098739

ISBN: (纸本)9783319098739;9783319098722

Nowadays, HPC systems frequently emerge as clusters of commodity processors with attached accelerators. Moving from tedious low-level accelerator programming to increased development productivity, the directive-based programming models OpenACC and OpenMP are promising candidates. While OpenACC was completed about two years ago, OpenMP just recently added support for accelerator programming. To assist developers in their decision-making which approach to take, we compare both models with respect to their programmability. Besides investigating their expressiveness by putting their constructs side by side, we focus on the evaluation of their power based on structured parallel programming patterns (aka algorithmic skeletons). These patterns describe the basic entities of parallel algorithms of which we cover the patterns map, stencil, reduction, fork-join, superscalar sequence, nesting and geometric decomposition. Architectural targets of this work are NVIDIA-type accelerators (GPUs) and specialties of Intel-type accelerators (Xeon Phis). Additionally, we assess the prospects of OpenACC and OpenMP concerning future development in soft-and hardware design.

关键词： OpenACC OpenMP 4 GPU Xeon Phi programmability parallel patterns

来源：评论

学校读者我要写书评

暂无评论

Automatic parallel Pattern Detection in the Algorithm Structure Design Space 30

Automatic Parallel Pattern Detection in the Algorithm Struct...

引用

30th IEEE International parallel and Distributed Processing Symposium (IPDPS)

作者： Huda, Zia Ul Atre, Rohit Jannesari, Ali Wolf, Felix Tech Univ Darmstadt Lab Parallel Programming Darmstadt Germany Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781509021406

parallel design patterns have been developed to help programmers efficiently design and implement parallel applications. However, identifying a suitable parallel pattern for a specific code region in a sequential application is a difficult task. Transforming an application according to support structures applicable to these parallel patterns is also very challenging. In this paper, we present a novel approach to automatically find parallel patterns in the algorithm structure design space of sequential applications. In our approach, we classify code blocks in a region according to the appropriate support structure of the detected pattern. This classification eases the transformation of a sequential application into its parallel version. We evaluated our approach on 17 applications from four different benchmark suites. Our method identified suitable algorithm structure patterns in the sequential applications. We confirmed our results by comparing them with the existing parallel versions of these applications. We also implemented the patterns we detected in cases in which parallel implementations were not available and achieved speedups of up to 14x.

关键词： parallelism parallel patterns task parallelism

来源：评论

学校读者我要写书评

暂无评论

A formal CSP framework for message-passing HPC programming

A formal CSP framework for message-passing HPC programming

引用

19th IEEE Canadian Conference on Electrical and Computer Engineering

作者： Carter, J. Gardner, W. B. Univ Guelph Dept Comp & Informat Sci Guelph ON N1G 2W1 Canada

ISBN: (纸本)9781424400379

To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), which has a strict semantics for interprocess communication and synchronization. Verification tools are available for CSP-specified programs to prove the absence of failures such as deadlock, and to explore potential multiprocess interactions. By introducing a CSP abstraction layer on top of the popular MPI message passing primitives, we create a framework, called CSP4MPI, designed to largely hide the complexity of parallel programming for HPC. CSP4MPI is comprised of a C++ class library that provides a CSP-based process model, and a "cookbook" of candidate solutions for HPC programmers not trained in CSP. Developers can prototype their systems using CSP, and use verification tools to examine possible points of failure before implementing via the CSP4MPI library. Alternatively, they may choose an existing, verified solution from a number of common parallel application archetypes. By using CSP4MPI, HPC developers leverage the benefits of formal specification and verification in their work, in addition to obtaining an alternate method to developing HPC applications.

关键词： HPC MPI parallel patterns CSP selective formalism

来源：评论

学校读者我要写书评

暂无评论

Streaming Dynamic Coarse-Grained CPU/GPU Workloads with Heterogeneous Pipelines in FastFlow

Streaming Dynamic Coarse-Grained CPU/GPU Workloads with Hete...

引用

14th IEEE International Conference on High Performance Computing and Communications (HPCC) / IEEE 9th International Conference on Embedded Software and Systems (ICESS)

作者： Goli, Mehdi Garba, Michael T. Gonzalez-Velez, Horacio Robert Gordon Univ IDEAS Res Inst Aberdeen AB9 1FR Scotland

ISBN: (纸本)9780769547497

Software pipelines permit the decomposition of a repetitive sequential process into a succession of distinguishable sub-processes called stages, each of which can be concurrently executed on a distinct processing element. This paper presents a heterogeneous streaming pipeline implementation using the FastFlow skeletal library for a numerical linear algebra code. By introducing minimal memory management, we implement a large-scale streaming application which allocates the different pipeline stages to multi-core CPU and multi-GPU resources in a cluster environment, demonstrating the suitability of the algorithmic skeleton approach to efficiently coordinate the pipeline operation. Our implementation shows that long-running heterogeneous pipelines can be effectively implemented in FastFlow.

关键词： Algorithmic Skeletons parallel patterns GPU parallel Programming Cluster Computing

来源：评论

学校读者我要写书评

暂无评论

Automatic Mapping of parallel Pattern-Based Algorithms on Heterogeneous Architectures 34th

Automatic Mapping of Parallel Pattern-Based Algorithms on He...

引用

34th International Conference on Architecture of Computing Systems (ARCS)

作者： Truemper, Lukas Miller, Julian Terboven, Christian Mueller, Matthias S. Huddly AS Oslo Norway Rhein Westfal TH Aachen IT Ctr Chair High Performance Comp Aachen Germany

ISBN: (纸本)9783030816827;9783030816810

Nowadays, specialized hardware is often found in clusters to improve compute performance and energy efficiency. The porting and tuning of scientific codes to these heterogeneous clusters requires significant development efforts. To mitigate these efforts while maintaining high performance, modern parallel programming models introduce a second layer of abstraction, where an architecture-agnostic source code can be maintained and automatically optimized for the target architecture. However, with increasing heterogeneity, the mapping of an application to a specific architecture itself becomes a complex decision requiring a differentiated consideration of processor features and algorithmic properties. Furthermore, architecture-agnostic global transformations are necessary to maximize the simultaneous utilization of different processors. Therefore, we introduce a combinatorial optimization approach to globally transform and automatically map parallel algorithms to heterogeneous architectures. We derive a global transformation and mapping algorithm which bases on a static performance model. Moreover, we demonstrate the approach on five typical algorithmic kernels showing automatic and global transformations such as loop fusion, re-ordering, pipelining, NUMA awareness, and optimal mapping strategies to an exemplary CPU-GPU compute node. Our algorithm achieves performance on par with hand-tuned implementations of all five kernels.

关键词： Mapping Heterogeneous architectures Global transformations parallel patterns Performance portability

来源：评论

学校读者我要写书评

暂无评论

TOWARDS THE DEPLOYMENT OF FASTFLOW ON DISTRIBUTED VIRTUAL ARCHITECTURES

TOWARDS THE DEPLOYMENT OF FASTFLOW ON DISTRIBUTED VIRTUAL AR...

引用

27th European Conference on Modelling and Simulation, ECMS 2013

作者： Campa, Sonia Danelutto, Marco Torquati, Massimo Gonzalez-Velez, Horacio Popescu, Alina Madalina Univ Pisa Dept Comp Sci I-56100 Pisa Italy Natl Coll Ireland Cloud Competency Ctr Dublin Ireland

ISBN: (纸本)9780956494467

In this paper we investigate the deployment of Fast Flow applications on multi-core virtual platforms. The overhead introduced by the virtual environment has been measured using a well-known application benchmark both in the sequential and in the Fast Flow parallel setting. The overhead introduced for both the sequential and the parallel executions of CPU and memory-intensive applicatiotis is in the range of 2 - 30%, while the execution speedup is almost preserved. Additionally, we have ported the FastFlow benchmark to a cloud-based distributed environment in which a task-intensive application has been tested and the performance compared with the corresponding run on a smaller cluster of multi-core machines without virtualisation. From a parallel programming perspective, we have demonstrated how a unique programming framework based on the structured parallel programming paradigm can cope with very different kind of target architectures without any (or minimal) code intervention.

关键词： parallel patterns Algorithmic Skeletons Language Constructs and Features parallel Programming Distributed Architectures Performance Analysis Virtualisation Cloud Computing

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of Multi-Threaded Algorithms in Polynomial Algebra 21

Design and Implementation of Multi-Threaded Algorithms in Po...

引用

46th International Symposium on Symbolic and Algebraic Computation, ISSAC 2021

作者： Moreno Maza, Marc University of Western Ontario LondonON Canada

来源：评论

学校读者我要写书评

暂无评论

Raising the parallel Abstraction Level for Streaming Analytics Applications

引用

IEEE ACCESS 2019年 7卷 131944-131961页

作者： Mencagli, Gabriele Torquati, Massimo Griebler, Dalvan Danelutto, Marco Fernandes, Luiz Gustavo L. Univ Pisa Dept Comp Sci I-56127 Pisa Italy Pontifical Catholic Univ Rio Grande do Sul PUCRS Sch Technol BR-90619900 Porto Alegre RS Brazil

In the stream processing domain, applications are represented by graphs of operators arbitrarily connected and filled with their business logic code. The APIs of existing Stream Processing Systems (SPSs) ease the development of transformations that recur in the streaming practice (e.g., filtering, aggregation and joins). In contrast, their parallelism abstractions are quite limited since they provide support to stateless operators only, or when the state is organized in a set of key-value pairs. This paper presents how the parallel patterns methodology can be revisited for sliding-window streaming analytics. Our vision fosters a design process of the application as composition and nesting of ready-to-use patterns provided through a C++17 fluent interface. Our prototype implements the run-time system of the patterns in the FastFlow parallel library expressing thread-based parallelism. The experimental analysis shows interesting outcomes. First, our pattern-based approach allows easy prototyping of different versions of the application, and the programmer can leverage nesting of patterns to increase performance (up to 37% in one of the two considered test-bed cases). Second, our FastFlow implementation outperforms (three times faster) the handmade porting of our patterns in popular JVM-based SPSs. Finally, in the concluding part of this paper, we explore the use of a task-based run-time system, by deriving interesting insights into how to make our patterns library suitable for multi backends.

关键词： Data stream processing streaming analytics sliding-window queries parallel patterns multicore programming

来源：评论

学校读者我要写书评

暂无评论

parallel Pattern Compiler for Automatic Global Optimizations

引用

parallel COMPUTING 2024年 122卷

作者： Schmitz, Adrian Burak, Semih Miller, Julian Mueller, Matthias S. Rhein Westfal TH Aachen IT Ctr Aachen Germany

High-performance computing (HPC) systems enable scientific advances through simulation and data processing. The heterogeneity in HPC hardware and software increases the application complexity and reduces its maintainability and productivity. This work proposes a prototype implementation for a parallel pattern-based source-to-source compiler to address these challenges. The prototype limits the complexity of parallelism and heterogeneous architectures to parallel patterns that are optimized towards a given target architecture. By applying high-level optimizations and a mapping between parallel patterns and execution units during compile time, portability between systems is achieved. The compiler can address architectures with shared memory, distributed memory, and accelerator offloading. The approach shows speedups for seven of the nine supported Rodinia benchmarks, reaching speedups of up to twelve times. Porting LULESH to the parallel Pattern Language (PPL) shows a compression of code size by 65% (3.4 thousand lines of code) through a more concise expression and a higher level of abstraction. The tool's limitations include dynamic algorithms that are challenging to analyze statically and overheads during the compile time optimization. This paper is an extended version of a previous PMAM publication (Schmitz et al., 2024).

关键词： parallel patterns Shared memory GPU offloading Distributed systems code generation productivity

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：