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A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements

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MICROELECTRONICS JOURNAL 2019年第Jun.期88卷 37-46页

作者： Rahimi, M. Ghaznavi-Ghoushchi, M. B. Shahed Univ Sch Engn Dept EE Tehran Iran

A new comparator based on the parallel prefix (PP) tree is presented. The improvement is utilized in both of algorithmic-level and cell-elements. First the PP algorithm of comparator is improved and then a novel "XNOR-AND" circuit is presented to use in proposed comparator. According to modified PP, two comparators are presented with similar comparator algorithm and different circuits in pre-encoder steps. The pre-layout and post-layout simulations of all circuits are performed in 65 nm and 180 nm standard CMOS technologies. Simulations of 16, 32 and 64-bit comparators in TT-corner of 180 nm show that the improvement of PDP of proposedl(-proposed2) than conventional comparator are 35.62%(51.23%), 35.25%(49.80%) and 31.54%(45.37%), respectively. Also, the second proposed comparator circuit is investigated in Arithmetic Logic Unit (ALU). According to the simulation results, the improvement of PDP of ALU with proposed2 comparator than ALU with conventional comparator in 180 nm standard CMOS technology is 14.62%.

关键词： Binary comparator Digital arithmetic parallel prefix tree Pass transistor logic

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Design of High Speed Carry Select Adder using Modified parallel prefix Adder 8

Design of High Speed Carry Select Adder using Modified Paral...

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8th International Conference on Advances in Computing & Communications (ICACC)

作者： Hebbar, Abhishek R. Srivastava, Piyush Joshi, Vinod Kumar Manipal Acad Higher Educ Dept Elect & Commun Engn Manipal Inst Technol Manipal 576104 Karnataka India

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent Kung (BK), Ladner Fischer (LF) and Kogge Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BECCSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 tm CMOS technology. (C) 2018 The Authors. Published by Elsevier B.V.

关键词： CSLA parallel prefix tree Group PG logic BEC BK LF KS etc

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Design of High Speed Carry Select Adder using Modified parallel prefix Adder

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Procedia Computer Science 2018年 143卷 317-324页

作者： Abhishek R Hebbar Piyush Srivastava Vinod Kumar Joshi Department of Electronics and Communication Engineering Manipal Institute of Technology Manipal Academy of Higher Education Manipal 576104 Karnataka India

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

关键词： CSLA parallel prefix tree Group PG logic BEC BK LF KS etc

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Design and Implementation of Double Precision Floating Point Comparator

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Procedia Technology 2016年 25卷 528-535页

作者： P. Rony Antony Anjana Mary Joseph Assistant Professor Dept of ECE RSET Ernakulam 682039 India Student RSET Ernakulam 682039 India

Floating point comparison is a fundamental arithmetic operation in DSP processor. The high dynamic range of floating point comparators find wide applications in sorting data problem, DSP algorithms etc. High performance with optimum area is a major concern for the practical implementation of these comparators. Another major concern with respect to the floating point numbers is the invalid numbers. Thus a separate module is required to handle the invalid numbers. In the present work, a double precision floating point comparator design is proposed for efficient floating point comparison. This comparator takes full advantage of the parallel prefix tree architecture. It first compares the most significant bit and proceeds towards least significant bit only when the compared bits are equal. Representation of floating point numbers is based on IEEE 754 standard. The double precision floating point comparator is modelled using Verilog HDL and synthesized in Xilinx ISE 14.6 targeting Virtex 5 and Cadence encounter tool. The results show that the new comparator architecture is efficient in handling all the invalid floating point numbers.

关键词： Floating point comparator Double precision parallel prefix tree

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A Novel Floating Point Comparator Using parallel tree Structure

A Novel Floating Point Comparator Using Parallel Tree Struct...

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International Conference on Circuit, Power and Computing Technologies (ICCPCT)

作者： Samuel, Anuja T. Senthilkumar, Jawahar Anna Univ ECE Dept Coll Engineeering Madras 600025 Tamil Nadu India

ISBN: (纸本)9781479970759

In recent years, floating point numbers are widely adopted due to its good robustness against quantization errors and high dynamic range capabilities. In this paper, a novel single-precision floating point comparator design is proposed. A parallel prefix tree structure is literally the back bone of this comparator design. This is designed using Verilog code, simulated and synthesised using CADENCE ENCOUNTER tool with TSMC 180nm technology. The proposed comparator fully supports single precision floating-point comparisons, as defined in the IEEE 754 standard. The proposed floating point comparator design exploits the advantages of structural reusability. Cadence Encounter synthesis for a 32-b floating point comparator shows a worst case input-output delay of 3.014 ns and a total power dissipation of 91.8 mu W using 0.18-mu m TSMC technology. The replacement of NOR-NAND gate using OR gate in the decision module incurs the improvement in the performance which thereby outperforms the existing design.

关键词： Floating point number parallel prefix tree IEEE 754 format

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Logic architecture for 2-select Arbiter using Duel Pointer 35

Logic architecture for 2-select Arbiter using Duel Pointer

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IEEE Region 10 Conference

作者： Kalpande, Mahesh D. Vyas, Vibha Coll Engn Pune Dept Elect Engn Pune Maharashtra India

ISBN: (纸本)9781479986415

Arbitration among various clients, requesting multiple resources simultaneously in high throughput system, needs multiple requests selection in single cycle. A new technique for implementation of arbiter, which selects up to two active request is proposed in this paper. 2 selector circuits are designed by modification of existing parallel prefix tree structures for architecture. Design maintains fairness among active requests by updating pointers according to grant selection algorithm presented. Simulation of design and comparison with previously work is done in terms of area and timing results.

关键词： Arbiter parallel prefix tree 2 selector Round Robin Method Priority encoder

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