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检索条件"主题词=Parallel Processing Systems"

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Efficient Layouts of Complete t-Partite and Complete Networks into 3-Ary n-Cubes for Optimized parallel processing in Multiprocessing systems

Efficient Layouts of Complete t-Partite and Complete Network...

引用

2024 IEEE International Conference on Signal processing, Informatics, Communication and Energy systems, SPICES 2024

作者： Rajeshwari, S. Rajesh, M. Sowmiya, C. Easwari Engineering College Department of Mathematics Chennai600 089 India Vellore Institute of Technology School of Computer Science and Engineering Chennai600 127 India

ISBN: (纸本)9798350376135

Embedding problems has received a lot of attention in the last decades by various research dealt with many inter-connection networks. Through embedding the existing parallel algorithm of an interconnection network can be used for the embedded network, thus it plays a vital role in manipulating the parallel algorithms of interconnection network in multiprocessing systems. A variation of the k-Ary n-cube, notable for its adaptive network structure created to provide efficient parallel processing on multicomputers, is the 3-Ary n-cube. In this study, complete t-partite graphs and complete graphs are embedded into 3-Ary n-cubes with the least wirelengths. © 2024 IEEE.

关键词： parallel processing systems

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parallel Computing for processing Data from Intelligent Transportation systems 10th

Parallel Computing for Processing Data from Intelligent Tran...

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10th International Conference on Supercomputing, ISUM 2019

作者： Denis, Jonathan Massobrio, Renzo Nesmachnow, Sergio Cristóbal, Alfredo Tchernykh, Andrei Meneses, Esteban Universidad de la República Montevideo Uruguay Universidad Veracruzana Heroica Veracruz Mexico Centro de Investigación Científica y Educación Superior de Ensenada Ensenada Mexico Centro Nacional de Alta Tecnología San José Costa Rica Instituto Tecnológico de Costa Rica Cartago Costa Rica

ISBN: (纸本)9783030380427

This article describes the application of parallel computing techniques for efficiently processing large volumes of data from ITS. This is a relevant problem in nowadays societies, especially when working under the novel paradigm of smart cities. The proposed approach applies parallel multithreading computing for processing Global Positioning System records for a case study on the Intelligent Transportation System in Montevideo, Uruguay. The experimental analysis is performed on a high performance computing platform, considering a large volume of data and different computing resources. The main results indicate that the proposed approach allows achieving good speedup values, thus reducing the execution time to process more than 120 GB of data from 921 to 77 min, when using 32 threads. In addition, a web application to illustrate the results of the proposed approach for computing the average speed of public transportation in Montevideo, Uruguay, is described. © Springer Nature Switzerland AG 2019.

关键词： parallel processing systems

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Temporal Fairness in Multiwinner Voting 38

Temporal Fairness in Multiwinner Voting

引用

38th AAAI Conference on Artificial Intelligence (AAAI) / 36th Conference on Innovative Applications of Artificial Intelligence / 14th Symposium on Educational Advances in Artificial Intelligence

作者： Elkind, Edith Obraztsova, Svetlana Teh, Nicholas Univ Oxford Oxford England Alan Turing Inst London England Carleton Univ Ottawa ON Canada

ISBN: (纸本)1577358872

Multiwinner voting captures a wide variety of settings, from parliamentary elections in democratic systems to product placement in online shopping platforms. There is a large body of work dealing with axiomatic characterizations, computational complexity, and algorithmic analysis of multiwinner voting rules. Although many challenges remain, significant progress has been made in showing existence of fair and representative outcomes as well as efficient algorithmic solutions for many commonly studied settings. However, much of this work focuses on single-shot elections, even though in numerous real-world settings elections are held periodically and repeatedly. Hence, it is imperative to extend the study of multiwinner voting to temporal settings. Recently, there have been several efforts to address this challenge. However, these works are difficult to compare, as they model multi-period voting in very different ways. We propose a unified framework for studying temporal fairness in this domain, drawing connections with various existing bodies of work, and consolidating them within a general framework. We also identify gaps in existing literature, outline multiple opportunities for future work, and put forward a vision for the future of multiwinner voting in temporal settings.

关键词： parallel processing systems

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3D-BBS: Global Localization for 3D Point Cloud Scan Matching Using Branch-and-Bound Algorithm

3D-BBS: Global Localization for 3D Point Cloud Scan Matching...

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IEEE International Conference on Robotics and Automation (ICRA)

作者： Aoki, Koki Koide, Kenji Oishi, Shuji Yokozuka, Masashi Banno, Atsuhiko Meguro, Junichi Meijo Univ Dept Mechatron Engn Tempaku Ku 1-501 Shiogamaguchi Nagoya Aichi 4688502 Japan Natl Inst Adv Ind Sci & Technol Dept Informat Technol & Human Factors Umezono 1-1-1 Tsukuba Ibaraki 3050061 Japan

ISBN: (纸本)9798350384581;9798350384574

This paper presents an accurate and fast 3D global localization method, 3D-BBS, that extends the existing branch-and-bound (BnB)-based 2D scan matching (BBS) algorithm. To reduce memory consumption, we utilize a sparse hash table for storing hierarchical 3D voxel maps. To improve the processing cost of BBS in 3D space, we propose an efficient roto-translational space branching. Furthermore, we devise a batched BnB algorithm to fully leverage GPU parallel processing. Through experiments in simulated and real environments, we demonstrated that the 3D-BBS enabled accurate global localization with only a 3D LiDAR scan roughly aligned in the gravity direction and a 3D pre-built map. This method required only 878 msec on average to perform global localization and outperformed state-of-the-art global registration methods in terms of accuracy and processing speed.

关键词： parallel processing systems

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MVSparse: Distributed Cooperative Multi-camera Multi-target Tracking on the Edge 20

MVSparse: Distributed Cooperative Multi-camera Multi-target ...

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20th IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS)

作者： Nalaie, Keivan Zheng, Rong McMaster Univ Hamilton ON Canada

ISBN: (纸本)9798350374292;9798350374285

Tracking people in multi-camera surveillance systems is challenging due to disparate perspectives, large volumes of data, and high computation demands. This paper presents a distributed cooperative pipeline for pedestrian tracking that exploits the spatial and temporal redundancy within and across the video feeds from multiple synchronized cameras. It consists of three key components: 1) a lightweight policy network trained online in a self-supervised manner on each camera, 2) a sparse backbone processing unit purpose-built for parallel processing of selected regions of all cameras, and 3) an online clustering algorithm for object association. Utilizing online distributed reinforcement learning, the fully end-to-end trainable pipeline can accelerate any tracking-by-detection method by reducing detection costs across multiple perspectives. MVSparse has been evaluated using two multi-camera multi-target pedestrian tracking datasets, WildTrack and MultiviewX. It reduces the amount of processed regions by up to 52% and 39% with only moderate degradation of 1% and 0.1% in tracking accuracy on the two datasets, respectively. On a real-world testbed comprising four NVIDIA Jetson TX2 and a GPU server, MVSparse accelerates the end-to-end process and reduces the communication overheads by 1.88 and 1.60 X with only 2.27% and 3.17% degradation in tracking accuracy on the two datasets, respectively.

关键词： parallel processing systems

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FastECPP over MPI 8th

FastECPP over MPI

引用

8th International Conference on Mathematical Software (ICMS)

作者： Enge, Andreas Univ Bordeaux INRIA CNRS CANARI F-33400 Talence France

ISBN: (纸本)9783031645280;9783031645297

The FastECPP algorithm is currently the fastest approach to prove the primality of general numbers, and has the additional benefit of creating certificates that can be checked independently and with a lower complexity. This article shows how by parallelising over a linear number of cores, its quartic time complexity becomes a cubic wallclock time complexity;and it presents the algorithmic choices of the FastECPP implementation in the author's Cm software https://www. ***/cm/ which has been written with massive parallelisation over MPI in mind, and which has been used to establish a new primality record for the "repunit" (10(86453) - 1)/9.

关键词： parallel processing systems

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Equivalence Testing: The Power of Bounded Adaptivity 27

Equivalence Testing: The Power of Bounded Adaptivity

引用

27th International Conference on Artificial Intelligence and Statistics (AISTATS)

作者： Chakraborty, Diptarka Chakraborty, Sourav Kumar, Gunjan Meel, Kuldeep S. Natl Univ Singapore Singapore Singapore Indian Stat Inst Kolkata India Univ Toronto Toronto ON Canada

Equivalence testing, a fundamental problem in the field of distribution testing, seeks to infer if two unknown distributions on [n] are the same or far apart in the total variation distance. Conditional sampling has emerged as a powerful query model and has been investigated by theoreticians and practitioners alike, leading to the design of optimal algorithms albeit in a sequential setting (also referred to as adaptive tester). Given the profound impact of parallel computing over the past decades, there has been a strong desire to design algorithms that enable high parallelization. Despite significant algorithmic advancements over the last decade, parallelizable techniques (also termed non-adaptive testers) have (O) over tilde (log(12) n) query complexity, a prohibitively large complexity to be of practical usage. Therefore, the primary challenge is whether it is possible to design algorithms that enable high parallelization while achieving efficient query complexity. Our work provides an affirmative answer to the aforementioned challenge: we present a highly parallelizable tester with a query complexity of (O) over tilde (log n), achieved through a single round of adaptivity, marking a significant stride towards harmonizing parallelizability and efficiency in equivalence testing.

关键词： parallel processing systems

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Limited Memory Online Gradient Descent for Kernelized Pairwise Learning with Dynamic Averaging 38

Limited Memory Online Gradient Descent for Kernelized Pairwi...

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38th AAAI Conference on Artificial Intelligence (AAAI) / 36th Conference on Innovative Applications of Artificial Intelligence / 14th Symposium on Educational Advances in Artificial Intelligence

作者： AlQuabeh, Hilal de Vazelhes, William Gu, Bin Mohamed Bin Zayed Univ Artificial Intelligence Abu Dhabi U Arab Emirates Jilin Univ Sch Artificial Intelligence Jilin Peoples R China

ISBN: (纸本)1577358872

Pairwise learning, an important domain within machine learning, addresses loss functions defined on pairs of training examples, including those in metric learning and AUC maximization. Acknowledging the quadratic growth in computation complexity accompanying pairwise loss as the sample size grows, researchers have turned to online gradient descent (OGD) methods for enhanced scalability. Recently, an OGD algorithm emerged, employing gradient computation involving prior and most recent examples, a step that effectively reduces algorithmic complexity to O(T), with T being the number of received examples. This approach, however, con-fines itself to linear models while assuming the independence of example arrivals. We introduce a lightweight OGD algorithm that does not require the independence of examples and generalizes to kernel pairwise learning. Our algorithm builds the gradient based on a random example and a moving aver-age representing the past data, which results in a sub-linear regret bound with a complexity of O(T). Furthermore, through the integration of O((root) T log T) random Fourier features, the complexity of kernel calculations is effectively minimized. Several experiments with real-world datasets show that the proposed technique outperforms kernel and linear algorithms in offline and online scenarios.

关键词： parallel processing systems

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A Hardware-Software Design Framework for SpMV Acceleration with Flexible Access Pattern Portfolio 31

A Hardware-Software Design Framework for SpMV Acceleration w...

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31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025

作者： Wu, Zhenyu Wang, Maolin So, Hayden Kwok-Hay The University of Hong Kong Hong Kong AI Chip Center for Emerging Smart Systems Hong Kong The Hong Kong University of Science and Technology Hong Kong

ISBN: (纸本)9798331506476

Sparse matrix-vector multiplications (SpMV) are notoriously challenging to accelerate due to their highly irregular data access pattern. Although a fully customized static accelerator design may be adequate for small problems that can fit entirely within an on-chip memory buffer, practical SpMV problems are large and have dynamic matrix structures that cannot easily be optimized at compile time. To address this need for trade-off between flexibility and performance, we present SPASM, a hardware-software framework that accelerates SpMV computation using a customizable portfolio of data access patterns as templates and a reconfigurable hardware to support their run-time execution. SPASM extracts local data access patterns of the input matrices and derives a set of template patterns to encode these inputs. Subsequently, a novel hardware computing structure is proposed to support vectorized computation and flexible switching between different template patterns for each tile computation. Furthermore, SPASM leverages the global compositions of input matrices to derive hardware configuration and workload schedules that improve load balancing among the parallel processing units. Importantly, although SPASM can optimize the pattern portfolio for a particular set of expected input matrices, the generated hardware can flexibly be used to accelerate SpMV of different input patterns albeit with reduced performance. Experimental results show that SPASM can achieve an average 2.81 × speedup compared to the state-of-the-art SpMV accelerator while keeping a relatively low customization cost. © 2025 IEEE.

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Delinquent Loop Pre-execution Using Predicated Helper Threads 31

Delinquent Loop Pre-execution Using Predicated Helper Thread...

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31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025

作者： Seshadri, Anirudh Rotenberg, Eric North Carolina State University Department of Electrical and Computer Engineering United States

ISBN: (纸本)9798331506476

Branch pre-execution targets delinquent branches that are not predictable by conventional branch predictors. Helper threads attempt to resolve branches ahead of the main thread. Pre-executed branch outcomes are communicated to the main thread's fetch unit via a global branch queue or local branch queues (one per branch PC). Two key challenges are discussed in this paper. 1) Handling a delinquent branch b2 that is control-dependent on another delinquent branch b1. Prior works that include both branches resort to branch prediction of b1 in the helper thread to determine whether or not to pre-execute b2. But b1 is hard-to-predict and the misprediction bottleneck merely shifts from the main thread to the helper thread. 2) Handling a store instruction that both influences a delinquent branch and is control-dependent on it. We propose predicated helper threads (Phelps) to address these challenges. Phelps constructs a helper thread for each inner loop containing delinquent branches. All delinquent branches, even control-dependent ones (b2), are unconditionally pre-executed in each loop iteration. Per-branch queues are managed in lockstep based on loop iterations, allowing the helper thread to deposit outcomes for both b1 and b2 each iteration and the main thread to consume or ignore b2 outcomes in the correct sequence dictated by b1. The helper thread also retains influential stores for dynamic disambiguation and store-load forwarding. Any such store that is control-dependent on a delinquent branch is predicated on the branch's outcome, which is necessary because the helper thread no longer has control-flow (except for the loop branch). Phelps also features dual decoupled helper threads for outer-inner loop pairs, for effective branch pre-execution when the inner loop has a short and unpredictable trip count. © 2025 IEEE.

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