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1st Conference on Innovation in Technology and Engineering Science, CITES 2018

作者： Yunus, S. Dinata, U.G.S. Nazir, R. Aulia Electrical Engineering Department Universitas Andalas Pauh Padang25163 Indonesia Mechanical Engineering Department Universitas Andalas Pauh Padang25163 Indonesia

Operation of non-linear in an unbalance condition can cause harmonic problems in the power system. There are two parts in the use of computing time in harmonic load flow, the first in the construction of harmonic admittance matrix and the second is the iteration scheme for solving systems of linear equations. The solution technique of the harmonic admittance was developed as a parallel application, and a direct algorithm to calculate the admittance matrix elements. The three-phase power flow program is devided into three independent subproblems, namely: positive, negative, and zero sequence network. Positive sequence network had been been solved by using the Newton Raphson method without modifying their formulation. Negative and zero sequence networks had been solved using nodal voltage equation. All three sequence networks have been modeled by three independent circuits and solved simultaneously using multi-core processors in parallel programming. The results showed that the parallel three-phase load flow speed is higher than the sequential. © 2019 IOP Publishing Ltd.

关键词： parallel programming

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DtCraft: A High-Performance Distributed Execution Engine at Scale

DtCraft: A High-Performance Distributed Execution Engine at ...

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作者： Huang, Tsung-Wei Lin, Chun-Xun Wong, Martin D. F. Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign ChampaignIL61801 United States

Recent years have seen rapid growth in data-driven distributed systems, such as Hadoop MapReduce, Spark, and Dryad. However, the counterparts for high-performance or compute-intensive applications including large-scale optimizations, modeling, and simulations are still nascent. In this paper, we introduce DtCraft, a modern C++ based distributed execution engine to streamline the development of high-performance parallel applications. Users need no understanding of distributed computing and can focus on high-level developments, leaving difficult details, such as concurrency controls, workload distribution, and fault tolerance handled by our system transparently. We have evaluated DtCraft on both micro-benchmarks and large-scale optimization problems, and shown the promising performance from single multicore machines to clusters of computers. In a particular semiconductor design problem, we achieved 30 × speedup with 40 nodes and 15 × less development efforts over hand-crafted implementation. © 1982-2012 IEEE.

关键词： parallel programming

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Memory-Latency-Accuracy Trade-offs for Continual Learning on a RISC-V Extreme-Edge Node

arXiv

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arXiv 2020年

作者： Ravaglia, Leonardo Rusci, Manuele Capotondi, Alessandro Conti, Francesco Pellegrini, Lorenzo Lomonaco, Vincenzo Maltoni, Davide Benini, Luca DISI University of Bologna Italy DEI University of Bologna Italy FIM University of Modena and Reggio Emilia Italy IIS ETH Zurich Switzerland

AI-powered edge devices currently lack the ability to adapt their embedded inference models to the ever-changing environment. To tackle this issue, Continual Learning (CL) strategies aim at incrementally improving the decision capabilities based on newly acquired data. In this work, after quantifying memory and computational requirements of CL algorithms, we define a novel HW/SW extreme-edge platform featuring a low power RISC-V octa-core cluster tailored for on-demand incremental learning over locally sensed data. The presented multi-core HW/SW architecture achieves a peak performance of 2.21 and 1.70 MAC/cycle, respectively, when running forward and backward steps of the gradient descent. We report the trade-off between memory footprint, latency, and accuracy for learning a new class with Latent Replay CL when targeting an image classification task on the CORe50 dataset. For a CL setting that retrains all the layers, taking 5h to learn a new class and achieving up to 77.3% of precision, a more efficient solution retrains only part of the network, reaching an accuracy of 72.5% with a memory requirement of 300 MB and a computation latency of 1.5 hours. On the other side, retraining only the last layer results in the fastest (867 ms) and less memory hungry (20 MB) solution but scoring 58% on the CORe50 dataset. Thanks to the parallelism of the low-power cluster engine, our HW/SW platform results 25× faster than typical MCU device, on which CL is still impractical, and demonstrates an 11× gain in terms of energy consumption with respect to mobile-class solutions. Copyright © 2020, The Authors. All rights reserved.

关键词： parallel programming

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Rigel: A framework for openMP performancetuning 21

Rigel: A framework for openMP performancetuning

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21st IEEE International Conference on High Performance Computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Amarasinghe Baragamage, Piyumi Rameshka Senanayake, Pasindu Kannangara, Thulana Seneviratne, Praveen Jayasena, Sanath Patabandi, Tharindu Rusira Hall, Mary Dept of Computer Science AND Engineering University of Moratuwa Katubedda Sri Lanka School of Computing University of Utah Salt Lake CityUT United States

ISBN: (纸本)9781728120584

OpenMP allows developers to harness the power of shared memory multiprocessing in C and C++ applications, but the performance gained with OpenMP is highly sensitive to the underlying hardware, making performance portability across different hardware architectures fragile. For example, in mapping a parallel for loop to hardware, OpenMP 4 offers commands for exploiting vector instructions (simd directives) and automatic GPU offloading (target directives), as well as schedule directives for CPU load balancing. These benefits come with a cost. A developer has to be well aware of the architecture details, and the application, and must iteratively tune to determine the best combination of pragma directives delivering higher performance for the given target architecture. Hence in this paper we introduce Rigel, a framework that automates these decisions to arrive at optimized OpenMP annotated code. Given a code segment with inherent parallelism, our framework uses separate machine learning classification models to predict the anticipated benefit of each optimization. Both Vector Classification and GPU Offloading Classification models perform with average accuracies of 83%. Succeeding the classification process, code segments are optimized accordingly. Our results show that GPU offloading optimization lead to an average speedup of 8x over default non-optimized CPU parallel execution (pragma omp parallel for) and average Vector optimization speedup is 6x compared to LLVM Clang 4.0 auto-vectorization. Furthermore Scheduling mechanism selection process results in overall accuracy of 90%. © 2019 IEEE.

关键词： parallel programming

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Gadara: Dynamic deadlock avoidance for multithreaded programs 8

Gadara: Dynamic deadlock avoidance for multithreaded program...

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8th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2008

作者： Wang, Yin Kelly, Terence Kudlur, Manjunath Lafortune, Stéphane Mahlke, Scott EECS Department University of Michigan United States Hewlett-Packard Laboratories United States

ISBN: (纸本)9781931971652

Deadlock is an increasingly pressing concern as the multicore revolution forces parallel programming upon the average programmer. Existing approaches to deadlock impose onerous burdens on developers, entail high runtime performance overheads, or offer no help for unmodified legacy code. Gadara automates dynamic deadlock avoidance for conventional multithreaded programs. It employs whole-program static analysis to model programs, and Discrete Control Theory to synthesize lightweight, decentralized, highly concurrent logic that controls them at runtime. Gadara is safe, and can be applied to legacy code with modest programmer effort. Gadara is efficient because it performs expensive deadlock-avoidance computations offline rather than online. We have implemented Gadara for C/Pthreads programs. In benchmark tests, Gadara successfully avoids injected deadlock faults, imposes negligible to modest performance overheads (at most 18%), and outperforms a software transactional memory system. Tests on a real application show that Gadara identifies and avoids both previously known and unknown deadlocks while adding performance overheads ranging from negligible to 10%.

关键词： parallel programming

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Automating non-blocking synchronization in concurrent data abstractions 34

Automating non-blocking synchronization in concurrent data a...

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34th IEEE/ACM International Conference on Automated Software Engineering, ASE 2019

作者： Zhang, Jiange Yi, Qing Dechev, Damian University of Colorado Colorado SpringsCO United States

ISBN: (纸本)9781728125084

This paper investigates using compiler technology to automatically convert sequential C++ data abstractions, e.g., queues, stacks, maps, and trees, to concurrent lock-free implementations. By automatically tailoring a number of state-of-the-practice synchronization methods to the underlying sequential implementations of different data structures, our automatically synchronized code can attain performance competitive to that of manually-written concurrent data structures by experts and much better performance than heavier-weight support by software transactional memory (STM). © 2019 IEEE.

关键词： parallel programming

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Retrofiting parallelism onto ocaml

arXiv

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arXiv 2020年

作者： Sivaramakrishnan, K.C. Dolan, Stephen White, Leo Jaffer, Sadiq Kelly, Tom Sahoo, Anmol Parimala, Sudha Dhiman, Atul Madhavapeddy, Anil Iit Madras OCaml Labs Jane Street and University of Cambridge Computer Laboratory Opsian and OCaml Labs Iit Madras University of Cambridge Computer Laboratory OCaml Labs

OCaml is an industrial-strength, multi-paradigm programming language, widely used in industry and academia. OCaml is also one of the few modern managed system programming languages to lack support for shared memory parallel programming. This paper describes the design, a full-fedged implementation and evaluation of a mostly-concurrent garbage collector (GC) for the multicore extension of the OCaml programming language. Given that we propose to add parallelism to a widely used programming language with millions of lines of existing code, we face the challenge of maintaining backwards compatibility-not just in terms of the language features but also the performance of single-threaded code running with the new GC. To this end, the paper presents a series of novel techniques and demonstrates that the new GC strikes a balance between performance and feature backwards compatibility for sequential programs and scales admirably on modern multicore processors. Copyright © 2020, The Authors. All rights reserved.

关键词： parallel programming

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Road Recognition System with Heuristic Method and Machine Learning

Road Recognition System with Heuristic Method and Machine Le...

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International Conference of Advanced Informatics: Concept, Theory and Application (ICAICTA)

作者： Hagai Raja Sinulingga Rinaldi Munir School of Electrical Engineering and Informatics Institut Teknologi Bandung Medan Indonesia

ISBN: (纸本)9781728180397

Road recognition is one of essential information for determining an Autonomous Vehicle movement. Latest research has shown that machine learning could be used to obtain the information from images. Nevertheless, the system could be improved by effectivity and efficiency. This research proposed finding better feature combinations and using Artificial Neural Network algorithm to build higher accuracy road detection model for better effectivity. Region of Interest module using heuristic method also applied to reduce computation for better efficiency. These three new modules are implemented and combined with road recognition module to become road recognition system. The proposed method performance then tested and compared with the latest research. The experiment results shown that Artificial Neural Network cannot increase the system effectiveness. Nonetheless, with right feature and region of interest module, the proposed system successfully gives better performance. The prototype has accuracy increased from F1-score 0,94 to 0,95 and speed increased from 99 to 112 frames processed per second.

关键词： Machine learning algorithms parallel programming Roads Prototypes Artificial neural networks Streaming media Real-time systems

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A parallel-computing algorithm for high-energy physics particle tracking and decoding using GPU architectures

arXiv

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arXiv 2020年

作者： Declara, Placido Fernandez Cámpora Pérez, Daniel Hugo Garcia-Blas, Javier Bruch, Dorothea V.O.M. Garcia, J. Daniel Neufeld, Niko EP-LBC CERN Geneve 231211– Switzerland Department of Computer Science and Engineering University Carlos III of Madrid Madrid Spain Universidad de Sevilla ETSI Informática Av. Reina Mercedes s/n Sevilla41012 Spain LPNHE Sorbonne Université Paris Diderot Sorbonne Paris Cité CNRS/IN2P3 Paris France

Real-time data processing is one of the central processes of particle physics experiments which require large computing resources. The LHCb (Large Hadron Collider beauty) experiment will be upgraded to cope with a particle bunch collision rate of 30 million times per second, producing 109 particles/s. 40 Tbits/s need to be processed in real-time to make filtering decisions to store data. This poses a computing challenge that requires exploration of modern hardware and software solutions. We present Compass, a particle tracking algorithm and a parallel raw input decoding optimised for GPUs. It is designed for highly parallel architectures, data-oriented and optimised for fast and localised data access. Our algorithm is configurable, and we explore the trade-off in computing and physics performance of various configurations. A CPU implementation that delivers the same physics performance as our GPU implementation is presented. We discuss the achieved physics performance and validate it with Monte Carlo simulated data. We show a computing performance analysis comparing consumer and server grade GPUs, and a CPU. We show the feasibility of using a full GPU decoding and particle tracking algorithm for high-throughput particle trajectories reconstruction, where our algorithm improves the throughput up to 7.4× compared to the LHCb baseline. Copyright © 2020, The Authors. All rights reserved.

关键词： parallel programming

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CAPE: A checkpointing-based solution for OpenMP on distributed-memory architectures 1

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15th International Conference on parallel Computing Technologies, PaCT 2019

作者： Tran, Van Long Renault, Éric Ha, Viet Hai Hue Industrial College 70 Nguyen Hue Street Hue City Viet Nam SAMOVAR Télécom SudParis CNRS Université Paris-Saclay 9 rue Charles Fourier Evry Cedex91011 France College of Education Hue University Hue Viet Nam

ISBN: (数字)9783030256364

ISBN: (纸本)9783030256357

CAPE, which stands for Checkpointing-Aided parallel Execution, is a framework that automatically translates and provides runtime functions to execute OpenMP programs on distributed-memory architectures based on checkpointing techniques. In order to execute an OpenMP program on distributed-memory systems, CAPE uses a set of templates to translate an OpenMP source code into a CAPE source code which is then compiled using a regular C/C++ compiler. This code can be executed on distributed-memory systems under the support of the CAPE framework. This paper aims at presenting the design and implementation of a new execution model based on Time-stamp Incremental Checkpoints. The new execution model allows CAPE to use resources efficiently, avoid the risk of bottlenecks, overcome the requirement of matching the Bernstein’s conditions. As a result, these approaches make CAPE improving the performance, ability as well as reliability. © 2019, Springer Nature Switzerland AG.

关键词： parallel programming

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