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32nd IEEE International parallel and Distributed Processing Symposium (IPDPS)

作者： Ayres, Daniel L. Cummings, Michael P. Univ Maryland Ctr Bioinformat & Computat Biol College Pk MD 20742 USA

ISBN: (纸本)9781538655559

parallel computing algorithms benefit from increases in concurrency when the hardware capacity is being under utilized. For likelihood-based molecular evolution inferences this can be due to small problem sizes, or because hardware capacity has increased beyond dataset sizes. A central concept in this domain is a bifurcating tree, which represents evolutionary relationships. The topology of the tree being evaluated directly affects the degree of parallelism that can be exploited by likelihood-based algorithms. For time-reversible evolutionary models we can reroot an unbalanced tree in order to make it more symmetric, without affecting the likelihood. Based on the reduction in number of concurrent operation sets, we define a best-case theoretical expectations, based on tree size and topology, for speedup due to rerooting which approaches 2-fold as the number of tip nodes increases for pectinate trees, and much higher values for some random topologies as the number of tip nodes increases. Empirical results using the NVIDIA CUDA implementation of the BEAGLE library confirm the merit of this approach. For pectinate trees we observe speedups of up to 1.93-fold due to rerooting and even larger speedups for random trees for the core likelihood-evaluation function in BEAGLE.

关键词： Bayes methods Biology computing Evolution (biology) Phylogeny Maximum likelihood estimation Multicore processing parallel programming

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Laika: Efficient In-Place Scheduling for 3D Mesh Graph Computations 18

Laika: Efficient In-Place Scheduling for 3D Mesh Graph Compu...

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30th ACM Symposium on parallelism in Algorithms and Architectures (SPAA)

作者： Gruevski, Predrag Hasenplaugh, William Lugato, David Thomas, James J. Kensho Technol Inc Cambridge MA 02138 USA MIT CSAIL Cambridge MA 02139 USA CEA Cesta Le Barp France CS Stanford Stanford CA USA

ISBN: (纸本)9781450357999

Scientific computing problems are frequently solved using data-graph computations - algorithms that perform local updates on application-specific data associated with vertices of a graph, over many time steps. The data-graph in such computations is commonly a mesh graph, where vertices have positions in 3D space, and edges connect physically nearby vertices. A scheduler controls the parallel execution of the algorithm. Two classes of parallel schedulers exist: double-buffering and in-place. Double-buffering schedulers do not incur synchronization overheads due to an absence of read-write conflicts, but require two copies of the vertices, as well as a higher iteration count due to a slower convergence rate. Computations for which this difference in convergence rate is significant (e.g., multigrid method) are frequently performed using an in-place scheduler, which incurs synchronization overheads to avoid read-write conflicts on the single copy of vertex data. We present LAIKA, a deterministic in-place scheduler we created using a principled three-step design strategy for high-performance schedulers. LAIKA reorders the input graph using a Hilbert space-filling curve to improve cache locality and minimizes parallel coordination overhead by explicitly curbing excess execution parallelism. Consequently, Laika has significantly lower scheduling overhead than alternative in-place schedulers and is even faster per iteration than the parallel double-buffered implementation on a reordered input graph. We derive an improved bound on the expected number of cache misses incurred during a traversal of a graph reordered using a space-filling curve. We also prove that on a mesh graph G = (V, E), Laika performs O(vertical bar V vertical bar+vertical bar E vertical bar) total work and achieves linear expected speedup with P = O(vertical bar V vertical bar/log(2)vertical bar V vertical bar) workers. On 48 cores, LAIKA yields 38.4x parallel speedup and empirically fares well against co

关键词： Data-graph computations multithreading parallel programming scheduling work-stealing cache locality

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New Network / IT Command: Virtualized Function Performance for a Programmable Infrastructure

New Network / IT Command: Virtualized Function Performance f...

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作者： Veronica Karina Quintuna Rodriguez Sorbonne Universite

学位级别：博士

In the framework of Network Function Virtualization (NFV), we address in this work the performance analysis of virtualized network functions (VNFs), wherein the virtualization of the radio access network (namely, Cloud-RAN) is the driving use-case. The overarching principle of network virtualization consists of replacing network functions, which were so far running on dedicated and proprietary hardware, with open software applications running on shared general purpose servers. The complexity of virtualization is in the softwarization of low-layer network functions (namely, PHY functions) because their execution must meet strict latency requirements. Throughout this work, we evaluate the performance of VNFs in terms of latency which consid- ers the total amount of time that is required to process VNFs in cloud computing systems. We notably investigate the relevance of resource pooling and statistical multiplexing when available cores in a data center are shared by all active VNFs. We perform VNF modeling by means of stochastic service systems. Proposed queuing models reveal the behavior of high performance computing architectures based on parallel processing and enable dimensioning the required com- puting capacity in data centers.

关键词： Virtualization NFV VNF queuing systems resource pooling Cloud-RAN C-RAN parallel programming processor sharing cloud computing scheduling service chaining

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faimGraph: High Performance Management of Fully-Dynamic Graphs Under Tight Memory Constraints on the GPU

faimGraph: High Performance Management of Fully-Dynamic Grap...

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International Conference on High Performance Computing, Networking, Storage, and Analysis (SC)

作者： Winter, Martin Mlakar, Daniel Zayer, Rhaleb Seidel, Hans-Peter Steinberger, Markus Graz Univ Technol Graz Austria Max Planck Inst Informat Saarbrucken Germany

ISBN: (纸本)9781538683842

In this paper, we present a fully-dynamic graph data structure for the Graphics Processing Unit (GPU). It delivers high update rates while keeping a low memory footprint using autonomous memory management directly on the GPU. The data structure is fully-dynamic, allowing not only for edge but also vertex updates. Performing the memory management on the GPU allows for fast initialization times and efficient update procedures without additional intervention or reallocation procedures from the host. Our optimized approach performs initialization completely in parallel;up to 300x faster compared to previous work. It achieves up to 200 million edge updates per second for sorted and unsorted update batches;up to 30x faster than previous work. Furthermore, it can perform more than 300 million adjacency queries and millions of vertex updates per second. On account of efficient memory management techniques like a queuing approach, currently unused memory is reused later on by the framework, permitting the storage of tens of millions of vertices and hundreds of millions of edges in GPU memory. We evaluate algorithmic performance using a PageRank and a Static Triangle Counting (STC) implementation, demonstrating the suitability of the framework even for memory access intensive algorithms.

关键词： parallel programming GPU Massively parallel algorithms Dynamic graphs

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Partial differential equations preconditioner resilient to soft and hard faults

Partial differential equations preconditioner resilient to s...

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1st International Workshop on Fault Tolerant Systems (FTS)

作者： Rizzi, F. Morris, K. Sargsyan, K. Mycek, P. Safta, C. Le Maitre, O. Knio, O. Debusschere, B. Sandia Natl Labs Scalable Modeling & Anal Systems Livermore CA USA Sandia Natl Labs Digital & Quantum Info Syst Dept Livermore CA USA Sandia Natl Labs POB 969MS9152 Livermore CA 94551 USA Duke Univ Durham NC 27706 USA Duke Univ Mech Engn & Mat Sci Durham NC 27706 USA

ISBN: (纸本)9781467365994

We present a domain-decomposition-based preconditioner for the solution of partial differential equations (PDEs) that is resilient to both soft and hard faults. The algorithm reformulates the PDE as a sampling problem, followed by a solution update through data manipulation that is resilient to both soft and hard faults. This reformulation allows us to recast the problem as a set of independent tasks, and exploit data locality to reduce global communication. We discuss two different parallel implementations: (a) a single program multiple data (SPMD) version based on a one-to-one mapping between subdomain and MPI processes responsible for both state and computation;and (b) an asynchronous server-client implementation where all state information is held by the servers and clients are designed solely as computational units. We present a scalability comparison of both implementations under nominal conditions, showing efficiency within similar to 80% for up to 12,000 cores. We present a resilience analysis under different fault scenarios based on the server-client implementation. This framework provides resiliency to hard faults such that if a client crashes, it stops asking for work, and the servers simply distribute the work among all of the other clients alive. Erroneous subdomain solves (e.g. due to soft faults) appear as corrupted data, which is either rejected if that causes a task to fail, or is seamlessly filtered out during the regression stage through a suitable noise model. Three different types of faults are modeled: hard faults modeling nodes (or clients) crashing;soft faults occurring during the communication of the tasks between server and clients;and soft faults occurring during task execution. We demonstrate the resiliency of the approach for a 2D elliptic PDE, and explore the effect of the faults at various failure rates.

关键词： Resilience scientific computing supercomputers parallel programming distributed computing client-server systems high-performance computing parallel algorithms software engineering fault tolerance message passing fault-tolerant systems partial differential equations

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Real-time cortical simulation on neuromorphic hardware

arXiv

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arXiv 2019年

作者： Rhodes, Oliver Peres, Luca Rowley, Andrew G.D. Gait, Andrew Plana, Luis A. Brenninkmeijer, Christian Furber, Steve B. Department of Computer Science University of Manchester Manchester United Kingdom

Real-time simulation of a large-scale biologically representative spiking neural network is presented, through the use of a heterogeneous parallelisation scheme and SpiNNaker neuromorphic hardware. A published cortical microcircuit model is used as a benchmark test case, representing ≈ 1 mm2 of early sensory cortex, containing 77k neurons and 0.3 billion synapses. This is the first true real-time simulation of this model, with 10 s of biological simulation time executed in 10 s wall-clock time. This surpasses best published efforts on HPC neural simulators (3× slowdown) and GPUs running optimised SNN libraries (2× slowdown). Furthermore, the presented approach indicates that real-time processing can be maintained with increasing SNN size, breaking the communication barrier incurred by traditional computing machinery. Model results are compared to an established HPC simulator baseline to verify simulation correctness, comparing well across a range of statistical measures. Energy to solution, and energy per synaptic event are also reported, demonstrating that the relatively low-tech SpiNNaker processors achieve a 10× reduction in energy relative to modern HPC systems, and comparable energy consumption to modern GPUs. Finally, system robustness is demonstrated through multiple 12 h simulations of the cortical microcircuit, each simulating 12 h of biological time, and demonstrating the potential of neuromorphic hardware as a neuroscience research tool for studying complex spiking neural networks over extended time periods. Copyright © 2019, The Authors. All rights reserved.

关键词： parallel programming

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Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Archite...

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Proceedings of the 13th International Conference on Distributed Smart Cameras

作者： Walther Carballo-Hernández François Berry Maxime Pelcat Miguel Arias-Estrada Department of Images Perception Systems and Robotics Institut Pascal Aubière France Department of Images Institut National des Sciences Appliquées (INSA) des Rennes IETR UMR CNRS Rennes France Department of Computer Science Instituto Nacional de Astrofísica (Óptica y Electrónica (INAOE) Puebla Mexico

ISBN: (纸本)9781450371896

The success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. This task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, Processing Element (PE) and communication. This article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. The built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. The selected heterogeneous platform embeds an Nvidia® Jetson TX2 for the CPU-GPU side and an Intel Altera® Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. This test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Internet of Things Field Programmable Gate Array (FPGA) Graphic Processing Unit (GPU) Deep Learning (DL) Edge Computing Processing Elements (PE) Artificial Neural Networks (ANN) Single Instruction Multiple Data Convolutional Neural Networks (CNN) Models of Computation and Architecture Pipelining Heterogeneous Computing parallel programming

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ParaSail: A pointer-free pervasively-parallel language for irregular computations

arXiv

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arXiv 2019年

作者： Taft, S. Tucker AdaCore LexingtonMA United States

ParaSail is a language specifically designed to simplify the construction of programs that make full, safe use of parallel hardware even while manipulating potentially irregular data structures. As parallel hardware has proliferated, there has been an urgent need for languages that ease the writing of correct parallel programs. ParaSail achieves these goals largely through simplification of the language, rather than by adding numerous rules. In particular, ParaSail eliminates global variables, parameter aliasing, and most significantly, re-assignable pointers. ParaSail has adopted a pointer-free approach to defining complex data structures. Rather than using pointers, ParaSail supports flexible data structuring using expandable (and shrinkable) objects implemented using region-based storage management, along with generalized indexing. By eliminating global variables, parameter aliasing, and pointers, ParaSail reduces the complexity for the programmer, while still allowing ParaSail to provide flexible, pervasive, safe, parallel programming for irregular computations. Perhaps the most interesting discovery in this language development effort, based on over six years of use by the author and a group of ParaSail users, has been that it is possible to simultaneously simplify the language, support parallel programming with advanced data structures, and maintain flexibility and efficiency. Copyright © 2019, The Authors. All rights reserved.

关键词： parallel programming

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Executable Modelling for Highly parallel Accelerators

Executable Modelling for Highly Parallel Accelerators

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ACM/IEEE International Conference on Model Driven Engineering Languages and Systems Companion

作者： Lorenzo Addazi Federico Ciccozzi Bjorn Lisper School of Innovation Design and Engineering Malardalen University

ISBN: (纸本)9781728151267

High-performance embedded computing is developing rapidly since applications in most domains require a large and increasing amount of computing power. On the hardware side, this requirement is met by the introduction of heterogeneous systems, with highly parallel accelerators that are designed to take care of the computation-heavy parts of an application. There is today a plethora of accelerator architectures, including GPUs, many-cores, FPGAs, and domain-specific architectures such as AI accelerators. They all have their own programming models, which are typically complex, low-level, and involve explicit parallelism. This yields error-prone software that puts the functional safety at risk, unacceptable for safety-critical embedded applications. In this position paper we argue that high-level executable modelling languages tailored for parallel computing can help in the software design for high performance embedded applications. In particular, we consider the data-parallel model to be a suitable candidate, since it allows very abstract parallel algorithm specifications free from race conditions. Moreover, we promote the Action Language for fUML (and thereby fUML) as suitable host language.

关键词： parallel programming fUML Alf UML Modelling languages High-performance computing Data-parallelism Executable models High Performance Computing parallel programming modelling languages UML data parallel computational power Accelerators GTF2A1L gene Software design Accelerator architectures embedded application Position Papers HETEROGENEOUS SYSTEM

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parallel solver for the Poisson equation on a hierarchy of superimposed meshes, under a Python framework

Parallel solver for the Poisson equation on a hierarchy of s...

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作者： Par Federico Tesser UNIVERSITE DE BORDEAUX

学位级别：博士

Adaptive discretizations are important in compressible/incompressible flow problems since it is often necessary to resolve details on multiple levels, allowing large regions of space to be modeled using a reduced number of degrees of freedom (reducing the computational time). There are a wide variety of methods for adaptively discretizing space, but Cartesian grids have often outperformed them even at high resolutions due to their simple and accurate numerical stencils and their superior parallel performances. Such performance and simplicity are in general obtained applying a finite-difference scheme for the resolution of the problems involved, but this discretization approach does not present, by contrast, an easy adapting path. In a finite-volume scheme, instead, we can incorporate different types of grids, more suitable for adaptive refinements, increasing the complexity on the stencils and getting a greater flexibility. The Laplace operator is an essential building block of the Navier-Stokes equations, a model that governs fluid flows, but it occurs also in differential equations that describe many other physical phenomena, such as electric and gravitational potentials, and quantum mechanics. So, it is a very important differential operator, and all the studies carried out on it, prove its relevance. In this work will be presented 2D finite-difference and finite-volume approaches to solve the Laplacian operator, applying patches of overlapping grids where a more fined level is needed, leaving coarser meshes in the rest of the computational domain. These overlapping grids will have generic quadrilateral shapes. Specifically, the topics covered will be: 1) introduction to the finite difference method, finite volume method, domain partitioning, solution approximation; 2) overview of different types of meshes to represent in a discrete way the geometry involved in a problem, with a focus on the octree data structure, presenting PABLO and PABLitO. The first one is an

关键词： Python Finite Differences Finite Volumes parallel programming Laplace Operator Adaptive Discretizations

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