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Enabling HW-Based Task Scheduling in Large Multicore Architectures

IEEE TRANSACTIONS ON COMPUTERS 2024年第1期73卷 138-151页

作者： Morais, Lucas Alvarez, Carlos Jimenez-Gonzalez, Daniel de Haro, Juan Miguel Araujo, Guido Frank, Michael Goldman, Alfredo Martorell, Xavier Barcelona Supercomp Ctr Barcelona 08034 Spain Univ Politecn Cataluna Barcelona 08034 Spain Univ Estadual Campinas BR-13083852 Campinas SP Brazil Arteris Inc Campbell CA 95008 USA Univ Sao Paulo BR-05508090 Sao Paulo Brazil

Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent parallelism. The performance of such solutions relies on the ability of the Task Scheduling HW/SW stack to efficiently evaluate dependencies at runtime and schedule work to available cores. Traditional SW-only systems implicate scheduling overheads of around 30K processor cycles per task, which severely limit the (core count, task granularity) combinations that they might adequately handle. Previous work on HW-accelerated Task Scheduling has shown that such systems might support high performance scheduling on processors with up to eight cores, but questions remained regarding the viability of such solutions to support the greater number of cores now frequently found in high-end SMP systems. The present work presents an FPGA-proven, tightly-integrated, Linux-capable, 30-core RISC-V system with hardware accelerated Task Scheduling. We use this implementation to show that HW Task Scheduling can still offer competitive performance at such high core count, and describe how this organization includes hardware and software optimizations that make it even more scalable than previous solutions. Finally, we outline ways in which this architecture could be augmented to overcome inter-core communication bottlenecks, mitigating the cache-degradation effects usually involved in the parallelization of highly optimized serial code.

关键词： parallel programming hardware acceleration Task Scheduling RISC-V custom ISA FPGA

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Load balanced sub-tree decomposition algorithm for solving Mixed Integer Linear programming models in behavioral synthesis

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COMPUTERS & ELECTRICAL ENGINEERING 2025年 123卷

作者： Fazlali, Mahmood Mirhosseini, Mina Moghaddam, Mahdi Movahedian Timarchi, Somayyeh Univ Hertfordshire Sch Phys Engn & Comp Sci Cybersecur & Comp Syst Res Grp Hatfield Herts England Shahid Beheshti Univ Fac Math Sci Dept Data & Comp Sci Tehran Iran Molde Univ Coll Fac Logest Molde Norway Queen Mary Univ London Sch Elect Engn & Comp Sci Antenna & Electromagnet Res Grp London E14NS England

Mixed Integer Linear programming (MILP) is utilized in behavioral synthesis as a mathematical model to design efficient hardware. However, solving large MILP models poses significant computational challenges due to their NP-hard nature. paralleling can tackle this challenge by amortizing the execution time, yet unbalanced loads can hinder its effectiveness. In this paper, we address the load balance issue of parallel Branch and Bound (B&B) algorithms, particularly sub-tree parallelism, which exhibit efficiency in solving MILP models derived from behavioral synthesis. The proposed algorithm strategically partitions the original problem into sub-problems by selecting decision variables that appear in a higher number of constraints to prioritize load balance and enhance solver performance. We evaluate the effectiveness of our method using MILP models derived from Mediabench data flow graphs of various sizes. The experimental results indicate that the proposed algorithm achieves speedups ranging from approximately 1 to 13 times, highlighting its efficacy in improving the scalability and efficiency of MILP solving for behavioral synthesis.

关键词： parallel programming MILP Load balancing Partitioning

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Self-Adaptive Micro-Batching for Low-Latency GPU-Accelerated Stream Processing

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INTERNATIONAL JOURNAL OF parallel programming 2025年第2期53卷 1-24页

作者： Leonarczyk, Ricardo Mencagli, Gabriele Griebler, Dalvan Pontif Catholic Univ Rio Grande Do Sul PUCRS Sch Technol Ave Ipiranga 6681 BR-90619900 Porto Alegre RS Brazil Univ Pisa Comp Sci Dept Largo Bruno Pontecorvo 3 I-56127 Pisa Italy

Stream processing is a computing paradigm enabling the continuous processing of unbounded data streams. Some classes of stream processing applications can greatly benefit from the parallel processing power and affordability offered by GPUs. However, efficient GPU utilization with stream processing applications often requires micro-batching techniques, i.e., the continuous processing of data batches to expose data parallelism opportunities and amortize host-device data transfer overheads. Micro-batching further introduces the challenge of finding suitable micro-batch sizes to maintain low-latency processing under highly dynamic workloads. The research field of self-adaptive software provides different techniques to address such a challenge. Our goal is to assess the performance of six self-adaptive algorithms in meeting latency requirements through micro-batch size adaptation. The algorithms are applied to a GPU-accelerated stream processing benchmark with a highly dynamic workload. Four of the six algorithms have already been evaluated using a smaller workload with the same application. We propose two new algorithms to address the shortcomings detected in the former four. The results demonstrate that a highly dynamic workload is challenging for the evaluated algorithms, as they could not meet the most strict latency requirements for more than 38.5% of the stream data items. Overall, all algorithms performed similarly in meeting the latency requirements. However, one of our proposed algorithms met the requirements for 4% more data items than the best of the previously studied algorithms, demonstrating more effectiveness in highly variable workloads. This effectiveness is particularly evident in segments of the workload with abrupt transitions between low- and high-latency regions, where our proposed algorithms met the requirements for 79% of the data items in those segments, compared to 33% for the best of the earlier algorithms.

关键词： parallel programming Heterogeneous architectures Self-adaptive algorithms GPU programming

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Supporting data decomposition in parallel programming

Supporting data decomposition in parallel programming

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作者： Meade, Anne University of Limerick

学位级别：master

parallelising serial software systems presents many challenges. In particular,the task of decomposing large, data-intensive applications for execution on distributedarchitectures is described in the literature as error-prone and *** Message Passing Interface (MPI) specification is the de facto industry standardto program for such architectures, but requires low level knowledge of datadistribution details as programmers must explicitly invoke inter-process communicationroutines. This research reports the findings from empirical studiesconducted in industry, to explore and characterise the challenges associated withperforming data decomposition. Findings from these studies culminated in alist of derived requirements for tool support, encompassing automation of gridindexing, generation of data structures and communication calls, and provisionof assistance when changing from an implemented decomposition strategy. Additionalrequirements include the need for a tool to be MPI focused, initiallytarget structured grids and have a low impact on the application code. Theserequirements were subsequently buttressed to address gaps in the state-of-the-artand provided motivation for the development of a tool named *** provides an abstraction for MPI, encapsulating the low level detailsinvolved in decomposing data and exchanging messages between *** can express the parallel intent of their application through input parametersand then generate code containing wrapper functions that encompass the MPIfunctionality. The wrapper functions can then be invoked within the serial coderesulting in a semi-automated parallelised solution. The programmer is relievedof the burden of deciphering memory locations when exchanging data betweenprocessors. The tool was evaluated in two studies involving both students andHigh Performance Computing (HPC) practitioners as subjects. The findingsconcluded that MPIGen provides an efficient abstraction for performing dat

关键词： software systems MPI parallel programming

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Shifted frequency analysis based, faster-than-real-time simulation of power systems on graphics processing unit

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INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2024年 159卷

作者： Zhang, Junjie Mittenbuehler, Marcel Benigni, Andrea Forschungszentrum Julich Wilhelm Johnen Str IEK-10 Energy Syst Engn D-52428 Julich Germany Univ Aachen RWTH Templergraben 55 D-52062 Aachen Germany JARA Energy D-52425 Julich Germany

In this paper we present a scalable approach based on the latency-based linear multistep compound method to use graphic processing unit (GPU) to accelerate the power system simulations with electromagnetic transients. To balance between the computational load and accuracy, we modeled the power system using shifted frequency analysis. Then, to efficiently exploit the hardware, our computational approach is designed to utilize both data-parallel and task-parallel execution. In addition, a graph-based thread safety design is introduced to achieve high scalability in the paralleled component computations. Furthermore, our implementation introduces a translation layer for different heterogeneous computing frameworks during compile time, so that a wide range of GPU devices can be supported without losing performance. Finally, benchmark results show that our approach achieves faster-than-real-time capability for systems with hundreds to thousands of nodes.

关键词： Graphics processing unit (GPU) Power system simulation parallel programming Shifted frequency analysis Dynamic phasor

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Refactoring for Java-Structured Concurrency

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APPLIED SCIENCES-BASEL 2025年第5期15卷 2407-2407页

作者： Zhang, Yang Shen, Gaojie Zhang, Liyan Zheng, Meiyan Zheng, Kun Hebei Univ Sci & Technol Sch Informat Sci & Engn Shijiazhuang 050000 Peoples R China

Structured concurrency treats multiple tasks running in different threads as a single unit, thereby improving reliability and enhancing observability. The existing IDE (Integrated Development Environment) does not provide sufficient support to leverage such an advanced structure and conduct refactoring automatically. Manual refactoring is tedious and error prone. There is an urgent need to provide adequate support to perform automatic refactoring. To this end, this paper proposes ReStruct, an automatic refactoring approach to transform unstructured concurrency to structured concurrency. ReStruct first employs visitor pattern analysis to acquire the target code for refactoring and then performs a precondition to filter out the code that meets the refactoring criteria. Subsequently, it performs scope analysis to guide the refactoring process. Finally, ReStruct performs refactoring on the AST of the source program. ReStruct is implemented as an Eclipse plugin and is evaluated in seven real-world projects via the number of refactorings and changes to LOCs (lines of code), time, and performance after refactoring. The experimental results illustrate that a total of 82 unstructured codes are refactored, with an average of 27.3 s per project. Furthermore, the performances of these refactored projects are improved by an average of 6.5%, demonstrating its effectiveness.

关键词： refactoring structured concurrency program analysis parallel programming

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GPotion: Embedding GPU programming in Elixir

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JOURNAL OF COMPUTER LANGUAGES 2025年 83卷

作者： Dubois, Andre Rauber Cavalheiro, Gerson Geraldo H. Univ Fed Pelotas UFPel Programa Posgrad Computacao PPGC Rua Gomes Carneiro 1 Pelotas RS Brazil

This paper describes GPotion, a DSL for GPU programming embedded in the Elixir functional language. GPotion allows programmers to write low-level GPU kernels, similar to CUDA kernels, in Elixir but also provides highlevel facilities, like garbage collection of host and device arrays allocated in the host, type inference and simplified data transfer. This paper describes the design and implementation of GPotion and also presents experiments that demonstrate that GPotion allows fast and efficient kernels with little overhead in comparison to pure CUDA. GPotion is implemented using metaprogramming features of Elixir, without having to modify Elixir's compiler. The source code for GPotion and the benchmarks used in the experiments are available in a GitHub repository.

关键词： parallel programming GPU DSL Elixir

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parallel programming OF A SYMMETRIC TRANSPORT-TRIGGERED ARCHITECTURE WITH APPLICATIONS IN FLEXIBLE LDPC ENCODING

PARALLEL PROGRAMMING OF A SYMMETRIC TRANSPORT-TRIGGERED ARCH...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Blaine Rister Pekka Jaaskelainen Olli Silven Jari Hannuksela Joseph R. Cavallaro Department of Electrical and Computer Engineering Rice University Houston Texas Department of Pervasive Computing Tampere University of Technology Tampere Finland Department of Computer Science and Engineering University of Oulu Oulu Finland

ISBN: (纸本)9781479928941

Exposed-datapath architectures yield small, low-power processors that trade instruction word length for aggressive compile-time scheduling and a high degree of instruction-level parallelism. In this paper, we present a general-purpose parallel accelerator consisting of a main processor and eight symmetric clusters, all in a single core. Use of a lightweight and memory-efficient application programming interface allows for the first high-performance program executing both sequential and data-parallel code on the same TTA processor. We use the processor for LDPC encoding, a popular method of forward error correction. Demonstrating the flexibility of software-defined radio, we benchmark the processor with two programs, one which can handle almost any sort of LDPC code, and another which is optimized for a specific standard. We achieve a throughput of 5 Mb/s with the flexible program and 92 Mb/s with the standard-specific one, while consuming only 95 mW at a clock frequency of 1175 MHz.

关键词： parallel programming low density parity check codes PROCESSOR clock frequency host processor FLEXIBLE ARCHITECTURE CENTROSYMMETRIC instruction-level parallelism Software radio Forward error correction Lightweight

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Celerity-RSim: Porting Light Propagation Simulation to Accelerator Clusters Using a High-Level API

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INTERNATIONAL JOURNAL OF parallel programming 2025年第3期53卷 1-24页

作者： Thoman, Peter Gschwandtner, Philipp Heredina, Facundo Molina Fahringer, Thomas Univ Innsbruck Innsbruck Austria PH3 GmbH Innsbruck Austria

Time-of-Flight (ToF) camera systems are increasingly capable of analyzing larger 3D spaces and providing more detailed and precise results. To increase the speed-to-solution during development, testing and validation of such systems, light propagation simulation is employed. One such simulation, RSim, was previously performed on single workstations, however, the increase in detail required for newer ToF hardware necessitates cluster-level parallelism in order to maintain an experiment latency which enables productive design work. Celerity is a high-level parallel API and runtime system for clusters of accelerators intended to simplify the development of domain science applications. It automatically manages data and work distribution, while also transparently enabling asynchronous compute and communication overlapping. In this paper, we present a use case study of porting the full RSim application to GPU clusters using the Celerity system. In order to improve scalability, a new parallelization scheme was employed for the core simulation task, and Celerity was extended with a high-level split constraints feature which enables this scheme. We present strong- and weak-scaling experiments for the resulting application on three accelerator clusters and up to 128 GPUs, and also evaluate the relative programming effort required to distribute the application on multiple GPUs using different APIs.

关键词： GPU computing Celerity SYCL Multi-gpu Distributed memory parallel programming HPC Light propagation Productivity

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Out of kernel tuning and optimizations for portable large-scale docking experiments on GPUs

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JOURNAL OF SUPERCOMPUTING 2024年第8期80卷 11798-11815页

作者： Accordi, Gianmarco Gadioli, Davide Vitali, Emanele Crisci, Luigi Cosenza, Biagio Beccari, Andrea Palermo, Gianluca Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy CSC IT Ctr Sci Espoo Finland Univ Salerno Dipartimento Informat Salerno Italy Dompe Farmaceut SpA Naples Italy

Virtual screening is an early stage in the drug discovery process that selects the most promising candidates. In the urgent computing scenario, finding a solution in the shortest time frame is critical. Any improvement in the performance of a virtual screening application translates into an increase in the number of candidates evaluated, thereby raising the probability of finding a drug. In this paper, we show how we can improve application throughput using Out-of-kernel optimizations. They use input features, kernel requirements, and architectural features to rearrange the kernel inputs, executing them out of order, to improve the computation efficiency. These optimizations' implementations are designed on an extreme-scale virtual screening application, named LiGen, that can hinge on CUDA and SYCL kernels to carry out the computation on modern supercomputer nodes. Even if they are tailored to a single application, they might also be of interest for applications that share a similar design pattern. The experimental results show how these optimizations can increase kernel performance by 2x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}, respectively, up to 2.2x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} in CUDA and up to 1.9x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}, in SYCL. Moreover, the reported speedup can be achieved with the best-proposed parameter

关键词： SYCL CUDA parallel programming Virtual screening HPC Performance Optimization GPU Batch computation Molecular docking

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