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Shared memory implementation and performance analysis of LSB steganography based on chaotic tent map

INNOVATIONS IN SYSTEMS AND SOFTWARE ENGINEERING 2021年第4期17卷 333-342页

作者： Gambhir, Gaurav Mandal, Jyotsna Kumar Univ Kalyani Kalyani 741235 W Bengal India

Concealing secret information in an image so that any perceptible evidence of the image alteration is insignificant, is known as image steganography. Image steganography can be implemented with either spatial or transform domain techniques. Spatial domain-based algorithms, generally the most widely used ones, refer to the process of embedding the secret information in the least significant bit positions of the cover image pixels. This paper proposes a chaotic tent map-based bit embedding as a novel steganography algorithm with a multicore implementation. The potential reasons for using chaotic maps in image steganography are sensitivity of these functions to initial conditions and control parameters. The computational complexity of the sequential least significant bit algorithm is known to be O(n). Hence, time complexity of the encryption/decryption algorithm is also a very important aspect. With the advantages offered by multicore processors, the proposed steganography algorithm can now be explicitly parallelized using the OpenMP API. As a pre-embedding operation, the quality of the randomness of the chaotic number sequences is tested with a NIST cryptographic test suite. The quality of the stego image is validated with statistical parameters such as structural similarity index (SSIM), mean square error (MSE) and peak signal-to-noise ratio (PSNR). Moreover, exploiting data parallelism inherent in the algorithm, multicore implementation of the algorithm with OpenMP API has also been reported. Proposed parallel version of the technique has been tested on five test samples of images for scalability analysis and results indicate significant speed up as compared to the sequential implementation of the technique.

关键词： OpenMP Performance measurement Performance analysis Steganography Cryptography parallel programming

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NPB-PSTL: C++ STL Algorithms with parallel Execution Policies in NAS parallel Benchmarks

NPB-PSTL: C++ STL Algorithms with Parallel Execution Policie...

引用

Euromicro Conference on parallel, Distributed and Network-Based Processing

作者： Júnior Löff Renato B. Hoffmann Arthur S. Bianchessi Leonardo Mallmann Dalvan Griebler Walter Binder Faculty of Informatics Università della Svizzera italiana (USI) Lugano Switzerland Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The C++ language continually evolves through formal specifications established by its standards committee, proposing new features to maintain $\mathrm{C}++$ as a relevant programming language while improving usability, performance, and portability across platforms. With the addition of parallel Standard Template Library (STL) algorithms in C++17, programmers can now leverage parallel processing capabilities via vendor-neutral parallel execution policies. This study presents an adaptation of the NAS parallel Benchmarks (NPB)—a well-established suite of applications for evaluating parallel architectures-by porting its sequential C-style code to use C++ STL abstractions and performance-portable parallelism features. Our goals are to (1) assess the suitability of C++ STL for scientific applications like the ones in the NPB and (2) provide a comparative performance and portability of STL algorithms’ parallel execution policies across different multicore architectures (x86 and AArch64). Results indicate that the performance of parallel STL algorithms is often close to that of optimized handwritten versions (OpenMP, Intel TBB, and FastFlow) on different architectures, with notable shortfalls. Across all NPB benchmarks, the STL algorithms’ geometric mean shows sequential execution times that are between 3.76% and $\mathrm{6. 9 \%}$ higher, while parallel executions may reach a geometric mean of up to $\mathrm{2 1. 2 1 \%}$ higher execution time.

关键词： parallel programming Multicore processing Software algorithms C++ languages Benchmark testing parallel processing Data structures Libraries Hardware Standards

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Popcorn: Accelerating Kernel K-means on GPUs through Sparse Linear Algebra

arXiv

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arXiv 2025年

作者： Bellavita, Julian Pasquali, Thomas Rio Martin, Laura Del Vella, Flavio Guidi, Giulia Cornell University IthacaNY United States University of Trento Trento Italy

K-means is a popular clustering algorithm with significant applications in numerous scientific and engineering areas. One drawback of K-means is its inability to identify non-linearly separable clusters, which may lead to inaccurate solutions in certain cases. Kernel K-means is a variant of classical K-means that can find non-linearly separable clusters. However, it scales quadratically with respect to the size of the dataset, taking several minutes to cluster even medium-sized datasets on traditional CPU-based machines. In this paper, we present a formulation of Kernel K-means using sparse-dense matrix multiplication (SpMM) and sparse matrix-vector multiplication (SpMV), and we show that our formulation enables the rapid implementation of a fast GPU-based version of Kernel K-means with little programming effort. Our implementation, named Popcorn, is the first open-source GPU-based implementation of Kernel K-means. Popcorn achieves a speedup of up to 123.8× over a CPU implementation of Kernel K-means and a speedup of up to 2.6× over a GPU implementation of Kernel K-means that does not use sparse matrix computations. Our results support the effectiveness of sparse matrices as tools for efficient parallel programming. © 2025, CC BY.

关键词： parallel programming

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HPC master design: experience from Pisa 33

HPC master design: experience from Pisa

引用

33rd Euromicro International Conference on parallel, Distributed, and Network-Based Processing, PDP 2025

作者： Danelutto, Marco Univ. of Pisa Dept. of Computer Science Italy

ISBN: (纸本)9798331524937

HPC is a widely used term, often referred to the applications, architectures and programming models and tools targeting highly parallel machines such as those of the *** lists. Recent advances in computing hardware resources require application of HPC techniques when using much smaller machines. Indeed, proper parallel programming tools and applications are needed also to exploit parallel hardware resources in personal computers (laptops, desktops, servers). This paper outlines key challenges in designing master's degree programs in HPC and shares lessons learned from various experiences in developing and implementing such programs in Italy and Europe. © 2025 IEEE.

关键词： parallel programming

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Application of CPU parallel Computing in MATLAB Environment for Analysis of Anti-Saturation and Gain Effects in PID Controller

Application of CPU Parallel Computing in MATLAB Environment ...

引用

Data Driven Control and Learning Systems (DDCLS)

作者： Ruirui Huang Zhenhui Wu Yandong Hou Qianshuai Cheng Henan Key Laboratory of Big Data Analysis and Processing Henan University Kaifeng China Technology and Media University of Henan Kaifeng Kaifeng China School of Artificial Intelligence Henan University Zhengzhou China

ISBN: (数字)9798350361674

ISBN: (纸本)9798350361681

With the continuous increase in data size and model complexity, the computational workload has grown rapidly, posing a significant challenge to the capabilities of computer data processing and simulation calculations. Therefore, parallel programming based on multicore and cluster architectures has become one of the mainstream technologies to enhance program execution efficiency and numerical computation efficiency. The theoretical foundations of parallel program computing have been applied in various aspects of engineering applications and theoretical simulations. In this paper, a new parallel PID anti-integral saturation controller is designed for a second-order closed-loop control system of unmanned aerial vehicles (UAVs). It compares and analyzes the runtime, execution efficiency, and speedup ratio of parallel programs and general serial programs under the same scenario. The experimental results demonstrate that parallel computing significantly improves the simulation program's efficiency for PID controller anti-saturation control systems under identical scenarios, exhibiting a high speedup ratio on the existing computing platform. Additionally, this study consolidates common issues encountered in MATLAB parallel program design, offering valuable insights into overcoming challenges in this domain.

关键词： Runtime parallel programming Multicore processing Process control parallel processing Control systems Central Processing Unit

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Accelerating Fortran Codes: A Method for Integrating Coarray Fortran with Cuda Fortran and Openmp

SSRN

引用

SSRN 2024年

作者： McKevitt, James Vorobyov, Eduard I. Kulikov, Igor University of Vienna Department of Astrophysics Türkenschanzstrasse 17 ViennaA-1180 Austria University College London Mullard Space Science Laboratory Holmbury St Mary Dorking SurreyRH5 6NT United Kingdom Institute of Computational Mathematics and Mathematical Geophysics SB RAS Lavrentieva ave. 6 Novosibirsk630090 Russia

Fortran's prominence in scientific computing requires strategies to ensure both that legacy codes are efficient on high-performance computing systems, and that the language remains attractive for the development of new high-performance codes. Coarray Fortran (CAF), an extension of Fortran introduced for parallel programming, facilitates distributed memory parallelism with a syntax familiar to Fortran programmers, simplifying the transition from single-processor to multi-processor coding. This research focuses on innovating and refining a parallel programming methodology that fuses the strengths of Intel Coarray Fortran, Nvidia CUDA Fortran, and OpenMP for distributed memory parallelism, high-speed GPU acceleration and shared memory parallelism respectively. We consider the management of pageable and pinned memory, CPU-GPU affinity in NUMA multiprocessors, and robust compiler interfacing with speed optimisation. We demonstrate our method through its application to a parallelised Poisson solver and compare the methodology, implementation, and scaling performance to that of the Message Passing Interface (MPI), finding CAF offers similar speeds with easier implementation. For new codes, this approach offers a faster route to optimised parallel computing. For legacy codes, it eases the transition to parallel computing, allowing their transformation into scalable, high-performance computing applications without the need for extensive re-design or additional syntax. © 2024, The Authors. All rights reserved.

关键词： parallel programming

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Etudes for parallel Programmers 33

Etudes for Parallel Programmers

引用

33rd Euromicro International Conference on parallel, Distributed, and Network-Based Processing, PDP 2025

作者： Marzolla, Moreno Center for Inter-Department Industrial Research ICT Bologna Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524937

Mini-applications are widely used in parallel computing for testing and benchmarking purposes. However, many existing mini-applications are not suitable for teaching, since they require advanced knowledge of algebra, numerical analysis or physics to be fully understood, which might be beyond the reach of beginners. In this paper we describe a set of programming assignments, called parallel etudes, that have been used in the last years for teaching High Performance Computing at the undergraduate level. These applications are self-contained, self-documenting, and short. They are drawn from more familiar domains such as 3D rendering, simulation, image processing and simple physics models, to be more accessible to students without a strong mathematical background. The mini-applications target shared-memory, distributed-memory and GPU programming. The analysis of the students' feedback and final grades provides indirect support for the effectiveness of the etudes. © 2025 IEEE.

关键词： parallel programming

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Enhancing Cluster Computing Performance through Big Data Techniques: A Survey on Scalability and Optimization

Enhancing Cluster Computing Performance through Big Data Tec...

引用

IEEE International Conference on Smart Cloud (SmartCloud)

作者： Smriti Kumari Pooja Rani Pallavi Joshi Computer Science and Engineering Texas A&M University Commerce Texas Department of CTECH SRMIST SRM University KTR Chennai India

ISBN: (数字)9798331596651

ISBN: (纸本)9798331596668

Cluster Computing Systems (CCS) is a type of technology that not only causes computing power improvement but also utilizes energy to a lesser degree by taking advantage of parallel programming while processing and reading massive amounts of data. We can have multiple Central Processing Units (CPUs) and storage devices (disks) where the massive size of data can be processed. However, Cluster Computing System also comes with its own set of challenges such as if for a reason the node stops operating, nodes stops communicating with each other and the data transfer doesn’t happen due to poor network which can lead to bottleneck while processing massive amounts of data. To overcome these issues, a well reputed tech giant known as Google, came up with a solution known as MapReduce. MapReduce is a framework designed for Big Data which takes care of processing large amounts of data over various servers. In this paper, we outline how CCS works and the challenges it faces today in the age of massive data. The introduction to some well received measures of Big Data are presented by us in this paper. These solutions show us the way we can address the issues we face in CSS. The primary goal of this writing is to look into the issues that we might face and the most efficient ways to resolve it in CSS.

关键词： Surveys parallel programming File systems Scalability Cluster computing Big Data Internet Servers Faces Optimization

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Teaching Performance Metrics in parallel Computing Courses

Teaching Performance Metrics in Parallel Computing Courses

引用

IEEE International Symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Sandino Vargas-Pérez Department of Computer Science Kalamazoo College Kalamazoo MI USA

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

As high-performance computing technologies advance, the significance of parallel programming in various domains is becoming increasingly evident since it allows us to harness the power of heterogeneous computing and solve complex problems more efficiently. However, for students to master this type of computation and be able to apply it in different contexts, it requires understanding how measuring and optimizing parallel code impacts its performance. This paper presents an approach to enhancing students' comprehension of parallel performance metrics through an interactive exercise that complements lectures on parallel performance and improves assessment.

关键词： Measurement Distributed processing Data analysis parallel programming High performance computing Conferences Education

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HPC master design: experience from Pisa

HPC master design: experience from Pisa

引用

Euromicro Conference on parallel, Distributed and Network-Based Processing

作者： Marco Danelutto Dept. of Computer Science Univ. of Pisa

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

HPC is a widely used term, often referred to the applications, architectures and programming models and tools targeting highly parallel machines such as those of the *** lists. Recent advances in computing hardware resources require application of HPC techniques when using much smaller machines. Indeed, proper parallel programming tools and applications are needed also to exploit parallel hardware resources in personal computers (laptops, desktops, servers). This paper outlines key challenges in designing master’s degree programs in HPC and shares lessons learned from various experiences in developing and implementing such programs in Italy and Europe.

关键词： Portable computers parallel programming High performance computing Europe parallel machines Hardware Telecommunications Stakeholders Servers programming profession

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