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A novel hardware implemented programmable controller adapted to cooperate with AI tuning algorithms in real time systems

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 2023年 428卷

作者： Talaska, Tomasz Dlugosz, Zofia Dlugosz, Rafal Bydgoszcz Univ Sci & Technol Fac Telecommun Comp Sci & Elect Engn Ul Kaliskiego 7 PL-85796 Bydgoszcz Poland

A novel, transistor level PID (proportional-integrating-derivative) controller is proposed that may be easily coupled with various AI algorithms responsible for adjusting its main factors. In our work we focus on a discrete-time digital approach, as it facilities realization a flexible and programmable structure that can be quickly re-configured depending on varying environment conditions. One of the novelties of the proposed solution is its parallel and asynchronous structure that requires only simple 2-phases clock. Each of the P, I and D blocks is realized as a separate channel with its own multi -bit multiplier, a summing circuit and a short delay line (in case of I and D blocks). The circuit features small chip area. For the input signals, and the coefficients of the controller being encoded as 8-bit signals the number of transistors does not exceed 13,000, which translates into the chip area not exceeding 0.1 mm2 in the CMOS 130 nm technology. Data rate of the controller can achieve 200-330 MSamples/s, with power dissipation not exceeding 1 mW. The proposed solution is suitable for miniaturized microsystems, for example high performance MEMS devices, in which small sizes and high data rate become very important features. (c) 2023 Elsevier B.V. All rights reserved.

关键词： Intelligent PID controller parallel and asynchronous signal processing Programmable circuits ASIC design

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