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33rd International Symposium on High-Performance parallel and Distributed Computing (HPDC)

作者： Nichols, Daniel Davis, Joshua H. Xie, Zhaojun Rajaram, Arjun Bhatele, Abhinav Univ Maryland Dept Comp Sci College Pk MD 20742 USA

ISBN: (纸本)9798400704130

Large language models are increasingly becoming a popular tool for software development. Their ability to model and generate source code has been demonstrated in a variety of contexts, including code completion, summarization, translation, and lookup. However, they often struggle to generate code for complex programs. In this paper, we study the capabilities of state-of-the-art language models to generate parallel code. In order to evaluate language models, we create a benchmark, PAREVAL, consisting of prompts that represent 420 different coding tasks related to scientific and parallel computing. We use PAREVAL to evaluate the effectiveness of several state-of-the-art open- and closed-source language models on these tasks. We introduce novel metrics for evaluating the performance of generated code, and use them to explore how well each large language model performs for 12 different computational problem types and six different parallel programming models.

关键词： Large language models parallel code generation Performance evaluation Benchmarking HPC

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A (Reverse) Mutation Testing Approach to Automatically generate parallel C/C plus plus code 30

A (Reverse) Mutation Testing Approach to Automatically gener...

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30th IEEE International Conference on Enabling Technologies - Infrastructure for Collaborative Enterprises (WETICE)

作者： Calanna, Salvatore Calvagna, Andrea Campisi, Salvatore Fornaia, Andrea Pappalardo, Giuseppe Torrisi, Riccardo Tramontana, Emiliano Univ Catania Dipartimento Matemat & Informat Catania Italy

ISBN: (纸本)9781665427890

As C/C++ has been widely used for several decades, a huge amount of C/C++ code is available. However, when using a modern processor having several cores, legacy code needs to be adapted for it to achieve the best performances. Modifying C/C++ code manually or automatically is not an easy task, given the complexity of the language. Moreover, it is paramount to check that the modified version keeps the emerging behaviour of the old one, except for the better performances. This paper proposes an automatic approach and the resulting tools to transform existing legacy C/C++ code for achieving parallel execution. The approach includes the automatic generation of test cases, customised for the code that has been converted into a parallel version. Test cases are auto-evaluating, hence a completely automatic cycle of code transformation, test generation, behavioural checking, has been achieved.

关键词： test case generation static analysis mutation testing parallel code generation

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Generating Efficient parallel code from the RVC-CAL Dataflow Language 22

Generating Efficient Parallel Code from the RVC-CAL Dataflow...

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45th Euromicro Conference on Software Engineering and Advanced Applications (SEAA) / 22nd Euromicro Conference on Digital System Design (DSD)

作者： Rafique, Omair Krebs, Florian Schneider, Klaus TU Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781728128610

The RVC-CAL language is used for implementing dataflow process networks (DPNs), i.e., distributed systems of actors. The behavior of an actor is defined by a set of actions which can consume input tokens and produce output tokens. RVC-CAL DPNs can offer parallelism both at the level of actors and at the level of actions. To efficiently execute these models on a target hardware, it is important to generate parallel code based on the entire parallelism provided by these two levels. In this paper, we discuss criteria for the generation of parallel software from RVC-CAL models based on the potential parallelism of modeled behaviors. The approach considers both the coarse-grained (task-parallel) execution of actors using multi-threading and the fine-grained (data-parallel) execution of their actions using the open computing language (OpenCL) or even a higher-level layer of OpenCL, namely SYCL. The methodology is validated by benchmarks on OpenCL abstracted hardware platforms. Based on the experimental results, the methodology is evaluated for efficiency (performance) in comparison with a pure multithreaded C++ approach and a well-known reference framework.

关键词： dataflow programming languages parallel code generation performance acceleration

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Communication Avoiding Algorithms: Analysis and code generation for parallel Systems 24

Communication Avoiding Algorithms: Analysis and Code Generat...

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24th International Conference on parallel Architecture and Compilation (PACT)

作者： Murthy, Karthik Mellor-Crummey, John Rice Univ Dept Comp Sci Houston TX USA

ISBN: (纸本)9781467395243

Data movement is a critical bottleneck for future generations of parallel systems. The class of .5D communication-avoiding algorithms were developed to address this bottleneck. These algorithms reduce communication and provide strong scaling in both time and energy. As a first step towards automating the development of communication-avoiding libraries, we developed the Maunam compiler. Maunam generates efficient parallel code from a high-level, global view sketch of .5D algorithms that are expressed using symbolic data sizes and numbers of processors. It supports the expression of data movement and communication through high-level global operations such as TILT and CSHIFT as well as through element-wise copy operations. With the latter, wraparound communication patterns can also be achieved using subscripts based on modulo operations. Maunam employs polyhedral analysis to reason about communication and computation present in a .5D algorithm. After partitioning data and computation, it inserts point-to-point and collective communication as needed. Maunam also analyzes data dependence patterns and data layouts to identify reductions over processor subsets. Maunam-generated Fortran+MPI code for 2.5D matrix multiplication running on 4096 cores of a Cray XC30 supercomputer achieves 59 TFlops/s (76% of the machine peak). Our generated parallel code achieves 91% of the performance of a hand-coded version.

关键词： Compilers polyhedral methods reductions modulo operations optimization parallel code generation

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Automated and parallel code generation for Finite-Differencing Stencils with Arbitrary Data Types

Automated and Parallel Code Generation for Finite-Differenci...

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International Conference on Computational Science (ICCS)

作者： Hawick, K. A. Playne, D. P. Massey Univ Auckland New Zealand

Finite-Differencing and other regular and direct approaches to solving partial differential equations (PDEs) are methods that fit well on data-parallel computer systems. These problems continue to arise in many application areas of computational science and engineering but still offer some programming challenges as they are not readily incorporated into a general standard software library that could cover all possible PDEs. Achieving high performance on numerical solutions to PDEs generally requires exposure of the field data structures and application of knowledge of how best to map them to the memory and processing architecture of a particular parallel computer system. Stencil methods for solving PDEs are however readily implemented as semi-automatically generated skeletal frameworks. We have implemented semi-automated stencil source code generators for a number of target programming languages including data-parallel languages such as CUDA for graphics processing units (GPUs). We report on some performance evaluations for our generated PDE simulations on GPUs and other platforms. In this article we focus on (diffusive) PDEs with a non-trivial data type requirement such as having vector or complex field variables. We discuss the issues and compromises involved implementing equation solvers with fields comprising arbitrary data types on GPUs and other current compute devices. (C) 2010 Published by Elsevier Ltd.

关键词： partial differential equation stencil parallel code generation GPU CUDA

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Automated and parallel code generation for finite-differencing stencils with arbitrary data types

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Procedia Computer Science 2010年第1期1卷 1795-1803页

作者： K.A. Hawick D.P. Playne Computer Science Massey University Albany North Shore 102-904 Auckland New Zealand

关键词： Partial differential equation Stencil parallel code generation GPU CUDA

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A Compiler Transformation to Overlap Communication with Dependent Computation 9

A Compiler Transformation to Overlap Communication with Depe...

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2015 9th International Conference on Partitioned Global Address Space Programming Models (PGAS)

作者： Murthy, Karthik Mellor-Crummey, John Rice Univ Houston TX 77251 USA

ISBN: (纸本)9781509001859

Hiding communication latency is essential to achieve scalable performance on current and future parallel systems. In this extended abstract, we present a novel compiler transformation that overlaps communication with computation to hide communication latency. Unlike prior work, we are able to achieve this overlap even in the presence of an overlap-inhibiting data dependence between the communication and computation. We do so by transforming the data dependence into an overlap-amenable one. To achieve this overlap, the Maunam compiler transforms the code by employing array expansion, partial loop peeling, loop alignment, and array contraction. This transformation is useful for optimization of systolic, communication avoiding algorithms.

关键词： Compilers communication-computation overlap loop alignment parallel code generation

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A parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems 17

A Parallelizing Matlab Compiler Framework and Run time for H...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Skalicky, Sam Lopez, Sonia Lukowiak, Marcin Schmidt, Andrew G. Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ Southern Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781479989379

Compute-intensive applications incorporate ever increasing data processing requirements on hardware systems. Many of these applications have only recently become feasible thanks to the increasing computing power of modern processors. The Matlab language is uniquely situated to support the description of these compute-intensive scientific applications, and consequently has been continuously improved to provide increasing computational support in the form of multithreading for CPUs and utilizing accelerators such as GPUs and FPGAs. Moreover, to take advantage of the computational support in these heterogeneous systems from the problem domain to the computer architecture necessitates a wide breadth of knowledge and understanding. In this work, we present a framework for the development of compute-intensive scientific applications in Matlab using heterogeneous processor systems. We investigate systems containing CPUs, GPUs, and FPGAs. We leverage the capabilities of Matlab and supplement them by automating the mapping, scheduling, and parallel code generation. Our experimental results on a set of benchmarks achieved from 20x to 60x speedups compared to the standard Matlab CPU environment with minimal effort required on the part of the user.

关键词： graphics processing units mathematics computing multi-threading parallel architectures parallelising compilers FPGA GPU Matlab compiler framework Matlab language compute-intensive scientific application computer architecture heterogeneous processor system heterogeneous system multithreading parallel code generation standard Matlab CPU environment Data transfer Field programmable gate arrays Kernel MATLAB Message systems Processor scheduling Scheduling Heterogeneous computing Matlab compiler MATLAB Multithreading Field programmable gate arrays HETEROGENEOUS SYSTEM Computer Architecture Computer based information systems mathematics computing compilers scheduling of multiprocessor code generation data transmission parallel architectures Graphics Processing Unit central processing units

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Enabling FPGA support in MATLAB based Heterogeneous Systems

Enabling FPGA support in MATLAB based Heterogeneous Systems

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Skalicky, Sam Kwolek, Tyler Lopez, Sonia Lukowiak, Marcin Rochester Inst Technol Rochester NY 14623 USA

ISBN: (纸本)9781479959440

FPGAs have been shown to provide orders of magnitude improvement over CPUs and GPUs in terms of absolute performance and energy efficiency for various kernels such as Cholesky decomposition, matrix inversion, and FFT among others. Despite this, the overall performance of many applications suffer when implemented entirely in FPGAs. Combining FPGAs with CPUs and GPUs provides the range of capabilities needed to support diverse computational requirements of applications. Integrating FPGAs into these systems challenges application developers with constructing hardware kernel implementations and interfacing from the low level hardware logic in the FPGA to the high speed networks that connect processors in the system. In this work we extend the compute capabilities of MATLAB by incorporating support for FPGAs and automating the parallel code generation. We characterize the system and evaluate the performance gains that can be achieved by adding the FPGA for two compute intensive applications. We present performance results for medical imaging and fluid dynamics applications implemented in a CPU+GPU+FPGA system and achieved up to 40x improvement compared to the standard MATLAB CPU+GPU environment.

关键词： computational fluid dynamics fast Fourier transforms field programmable gate arrays graphics processing units mathematics computing matrix inversion medical image processing multiprocessing systems parallel processing parallelising compilers CPU Cholesky decomposition FFT FPGA support GPU MATLAB based heterogeneous systems absolute performance application development computational requirements compute intensive application energy efficiency fluid dynamics application hardware kernel implementation high speed network low level hardware logic medical imaging parallel code generation performance gains processor connection Field programmable gate arrays Graphics processing units Hardware Instruction sets Kernel MATLAB

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YAPPA: a Compiler-Based parallelization Framework for Irregular Applications on MPSoCs

YAPPA: a Compiler-Based Parallelization Framework for Irregu...

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International Symposium on Rapid System Prototyping / Embedded Systems Week

作者： Lovergine, Silvia Tumeo, Antonino Villa, Oreste Ferrandi, Fabrizio Pacific NW Natl Lab Richland WA 99352 USA Politecn Milan DEIB Milan Italy

ISBN: (纸本)9781479924097

Modern embedded systems include hundreds of cores. Because of the difficulty in providing a fast, coherent memory architecture, these systems usually rely on non-coherent, non-uniform memory architectures with private memories for each core. However, programming these systems poses significant challenges. The developer must extract large amounts of parallelism, while orchestrating communication among cores to optimize application performance. These issues become even more significant with irregular applications, which present data sets difficult to partition, unpredictable memory accesses, unbalanced control flow and fine grained communication. Hand-optimizing every single aspect is hard and time-consuming, and it often does not lead to the expected performance. There is a growing gap between such complex and highly-parallel architectures and the high level languages used to describe the specification, which were designed for simpler systems and do not consider these new issues. In this paper we introduce YAPPA (Yet Another parallel Programming Approach), a compilation framework for the automatic parallelization of irregular applications on modern MPSoCs based on LLVM. We start by considering an efficient parallel programming approach for irregular applications on distributed memory systems. We then propose a set of transformations that can reduce the development and optimization effort. The results of our initial prototype confirm the correctness of the proposed approach.

关键词： Irregular Applications Compilers parallel code generation Embedded Systems HPC

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