检索结果-内蒙古大学图书馆

A Single and Adjacent Symbol Error-Correcting parallel decoder for Reed-Solomon Codes

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2015年第1期15卷 75-81页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba 2630022 Japan Northeastern Univ Dept Elect & Comp Engn Coll Engn Boston MA 02115 USA

This paper presents a novel high-speed Reed-Solomon (RS) decoder. The proposed decoder corrects in parallel adjacent and single-symbol errors;moreover, it serially corrects multiple-symbol errors other than adjacent errors. Its operation is based on a novel scheme that extends an existing binary BCH decoder such that a nonbinary RS code can be targeted. The proposed scheme, however, differs from previous schemes in the algorithm and construction of the parallel decoder;the proposed decoder is efficient for multilevel memory systems such as those utilizing phase change memory devices. Simulation results show that the proposed scheme requires a significantly smaller area and lower power than a traditional fully parallelized RS decoder capable of correcting any double-symbol errors in parallel. Furthermore, it is also shown that it requires a smaller area than a parallel error correction scheme using a nonbinary double-error-correcting orthogonal Latin square code.

关键词： Error correcting code (ECC) adjacent error correction (AEC) Reed-Solomon (RS) codes parallel decoder

来源：评论

学校读者我要写书评

暂无评论

A Single-Bit and Double-Adjacent Error Correcting parallel decoder for Multiple-Bit Error Correcting BCH Codes

引用

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2014年第2期14卷 664-671页

作者： Namba, Kazuteru Pontarelli, Salvatore Ottavi, Marco Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba 2638522 Japan Natl Interuniv Consortium Telecommun CNIT I-43124 Parma Italy Univ Roma Tor Vergata I-00173 Rome Italy Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

关键词： Error correcting code (ECC) double-adjacent error correction (DAEC) BCH codes parallel decoder

来源：评论

学校读者我要写书评

暂无评论

VQFR: Blind Face Restoration with Vector-Quantized Dictionary and parallel decoder 1

引用

17th European Conference on Computer Vision (ECCV)

作者： Gu, Yuchao Wang, Xintao Xie, Liangbin Dong, Chao Li, Gen Shan, Ying Cheng, Ming-Ming Nankai Univ CS TMCC Tianjin Peoples R China Tencent PCG ARC Lab Beijing Peoples R China Tencent Online Video Platform Technol Beijing Peoples R China Shanghai AI Lab Beijing Peoples R China Chinese Acad Sci Shenzhen Inst Adv Technol Beijing Peoples R China

ISBN: (数字)9783031197970

ISBN: (纸本)9783031197963;9783031197970

Although generative facial prior and geometric prior have recently demonstrated high-quality results for blind face restoration, producing fine-grained facial details faithful to inputs remains a challenging problem. Motivated by the classical dictionary-based methods and the recent vector quantization (VQ) technique, we propose a VQ-based face restoration method - VQFR. VQFR takes advantage of high-quality lowlevel feature banks extracted from high-quality faces and can thus help recover realistic facial details. However, the simple application of the VQ codebook cannot achieve good results with faithful details and identity preservation. Therefore, we further introduce two special network designs. 1). We first investigate the compression patch size in the VQ codebook and find that the VQ codebook designed with a proper compression patch size is crucial to balance the quality and fidelity. 2). To further fuse low-level features from inputs while not "contaminating" the realistic details generated from the VQ codebook, we proposed a parallel decoder consisting of a texture decoder and a main decoder. Those two decoders then interact with a texture warping module with deformable convolution. Equipped with the VQ codebook as a facial detail dictionary and the parallel decoder design, the proposed VQFR can largely enhance the restored quality of facial details while keeping the fidelity to previous methods.

关键词： Blind face restoration Vector quantization parallel decoder

来源：评论

学校读者我要写书评

暂无评论

Low-Complexity parallel Min-Sum Medium-Density Parity-Check decoder for McEliece Cryptosystem

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第12期70卷 5328-5338页

作者： Cai, Jiaxuan Zhang, Xinmiao Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA

The McEliece cryptosystem based on medium-density parity-check (MDPC) codes remains a candidate in the fourth round submission of post-quantum cryptography standard. The low-density parity-check (LDPC) decoders used in digital communications have been extensively studied. However, the MDPC codes for the McEliece cryptosystem have much higher column weight and different structure in their parity-check matrices. As a result, simplification techniques for LDPC decoders are not applicable to MDPC decoders. Besides, existing MDPC decoder designs have been focusing on the simplest bit-flipping algorithm, whose performance is inferior compared to that of the Min-sum algorithm. This paper first optimizes the scaled Min-sum algorithm for codes with high column weight to improve the performance with simple scalar multiplications. The overall decoder architecture is re-designed to take into account the sparsity of the parity-check matrix and nontrivial min-sum check node processing. Besides, a flexible message storage scheme is proposed to reduce the worst-case decoding latency of the randomly constructed codes utilized in the McEliece cryptosystem. Then a 2-stage scaling scheme is developed to reduce the long critical path caused by the high column weight and a group size re-balancing scheme is introduced to mitigate the precision loss caused by the 2-stage scaling in parallel decoders. For an example MDPC decoder, the proposed optimized 2-stage scaled Min-sum algorithm leads to orders of magnitude error-correcting performance improvement and 16% higher clock frequency with negligible silicon area overhead compared to unoptimized Min-sum decoders.

关键词： McEliece cryptosystem error-correcting codes medium-density parity-check codes min-sum algorithm parallel decoder post-quantum cryptography

来源：评论

学校读者我要写书评

暂无评论

Low-Latency parallel Row-Layered Min-sum MDPC decoder for McEliece Cryptosystem 37

Low-Latency Parallel Row-Layered Min-sum MDPC Decoder for Mc...

引用

2024 International Workshop on Signal Processing Systems

作者： Cai, Jiaxuan Zhang, Xinmiao Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA

ISBN: (纸本)9798350373769;9798350373752

In the latest round of post-quantum cryptography standardization, the McEliece cryptosystem utilizing medium-density parity-check (MDPC) codes remains a candidate. The row-layered Min-sum decoding for MDPC codes has better trade-off between performance and complexity. Previous work adds constraints to the parity-check matrix construction in order to enable efficient parallel decoding. However, the constraints for large parallelism cause an undesirable reduction in the number of usable secret keys and hence the previous scheme has limitations in achieving higher speed. This paper proposes two new schemes to substantially reduce the latency of row-layered MDPC decoding. Instead of further increasing the constraints to achieve higher parallelism, multiple identity blocks in the parity-check matrix are processed simultaneously in the first scheme and large blocks of variable width are processed in a hybrid way in the second design. Efficient hardware architectures are also developed for both proposed decoders. For an example code, the two proposed decoders achieve around 40% speedup compared to the best prior effort with less than 10% area overhead.

关键词： Error-correcting codes McEliece cryptosystem medium-density parity-check codes Min-sum algorithm parallel decoder post-quantum cryptography row-layered scheduling

来源：评论

学校读者我要写书评

暂无评论

Concurrent Error Detection of Binary and Nonbinary OLS parallel decoders

引用

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2014年第1期14卷 112-120页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba 2638522 Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults. Extensive simulation results are also provided;different figures of merit such as area, power dissipation, gate depth, and coverage are assessed. It is shown that the proposed decoder designs for (n, k) t-bit error correcting OLS codes (k = 16 ... 256;t = 2 ... 5) have reasonable overhead;for example, the average area overhead of the proposed CED is 35.5 (23.6) % compared with an OLS decoder with no CED (i.e., the previously reported CED scheme). However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation. The proposed CED is applicable to both binary and nonbinary OLS codes;the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder. Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy.

关键词： Error correcting code (ECC) concurrent error detection (CED) strongly fault secure (SFS) orthogonal Latin square (OLS) codes parallel decoder

来源：评论

学校读者我要写书评

暂无评论

A Novel Scheme for Concurrent Error Detection of OLS parallel decoders

A Novel Scheme for Concurrent Error Detection of OLS Paralle...

引用

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)9781479915859;9781479915835

This paper presents a concurrent error detection (CED) scheme for Orthogonal Latin Square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secure (SFS) for single stuck-at faults. Extensive simulation results are also provided: different figures of merit such as area, power dissipation, gate depth and coverage are assessed. It is shown that the proposed decoder designs for (n,k) t-bit error correcting OLS codes (k=16...256;t=2...5) have modest overheads. However, the most significant advantage of the proposed scheme is that it achieves 100 % fault coverage for the Is hole CED circuit, thus providing a very efficient and full fault tolerant implementation.

关键词： Error correcting code (ECC) concurrent error detection (CED) strongly fault secure (SFS) orthogonal Latin square (OLS) codes parallel decoder

来源：评论

学校读者我要写书评

暂无评论

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

引用

IEEE TRANSACTIONS ON COMPUTERS 2015年第7期64卷 2092-2097页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed (n symbols, k symbols) t-symbol error correcting code uses the same H matrix as an (n bits, k bits) binary t-bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.

关键词： Error correcting code (ECC) phase change memory (PCM) orthogonal Latin square (OLS) codes multi-symbol error correcting code parallel decoder

来源：评论

学校读者我要写书评

暂无评论

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level parallelism

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2021年第6期29卷 1083-1094页

作者： Kam, Dongyun Yoo, Hoyoung Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea Chungnam Natl Univ Dept Elect Engn Daejeon 34134 South Korea

Achieving the attractive error-correcting capability with a simple decoder structure, the polar code using successive cancellation (SC) decoding is now expected to be installed at the resource-limited IoT or embedded communications. However, the existing SC decoders normally suffer from the long processing latency caused by the serialized processing steps, limiting the practical applications of polar codes. In this article, to solve this latency problem, we present a new low-complexity merging operation that can increase the number of parallel factors for realizing the tree-level parallelism. We also modify the previous pruning method to further reduce the number of visited nodes at the parallel SC decoding scenario. In addition, a novel parallel partial-sum calculator (PSC) architecture is introduced to update partial-sum registers with multiple decoded bits by taking only one processing cycle. Implementation results show that the proposed 8-parallel SC polar decoder in 28-nm CMOS requires only 0.140 mu s to decode a (1024, 512) codeword of 5C system, remarkably reducing the decoding latency when compared to the state-of-the-art designs.

关键词： SC communications low-latency processing parallel decoder polar codes successive-cancellation decoding

来源：评论

学校读者我要写书评

暂无评论

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2013年第2期70卷 235-247页

作者： Cho, Junhee Sung, Wonyong Seoul Natl Univ Sch Elect Engn Seoul 151744 South Korea

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase-Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase-Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.

关键词： Turbo product code NAND flash memory Chase-Pyndiah decoding algorithm Soft-decision error correction parallel decoder

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：