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parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems

IEEE TRANSACTIONS ON COMPUTERS 2016年第12期65卷 3794-3801页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed;this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length;the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.

关键词： Error correcting code (ECC) unequal error protection (UEP) code approximate computing parallel decoder

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High-Speed parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2016年第1期16卷 30-37页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba 2638522 Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This paper presents a novel construction scheme for nonbinary single-error correcting (SEC) codes that yields highspeed parallel decoding. The proposed scheme utilizes two methods, namely, Improved and Reordered;these methods can be also combined. Both of these methods reduce the number of 1's in the parity-check matrix (H-matrix) by reducing the 1's in every row vector. This results in a reduction in the gate depth in the syndrome generator, thus achieving a shorter delay time for parallel decoding. In the proposed Improved method, for a single b-bit byte (i.e., 2(b)-ary symbol) error correcting code, the submatrix of the H-matrix corresponding to every b-bit byte is multiplied with a regular matrix. The so-called improved submatrix is generated using a heuristic (greedy) algorithm. The proposed Reordered method selects the correct b-bit bytes for deletion when shortening is performed. Simulation results show that the proposed scheme accomplishes a faster parallel decoding time than existing schemes. Furthermore, the proposed scheme is applicable to any class of linear SEC codes, whereas existing schemes are applicable only to specific codes. Extensive simulation results are provided to substantiate the viability of the proposed codes for faster parallel decoding (albeit incurring for most cases in modest increases of area and power dissipation due to additional circuitry).

关键词： Error correcting code (ECC) single error correction (SEC) non-binary codes parallel decoder

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A Real-Time License Plate Detection and Recognition Model in Unconstrained Scenarios

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SENSORS 2024年第9期24卷 2791页

作者： Tao, Lingbing Hong, Shunhe Lin, Yongxing Chen, Yangbing He, Pingan Tie, Zhixin Zhejiang Sci Tech Univ Sch Comp Sci & Technol Hangzhou 310018 Peoples R China Zhejiang Sci Tech Univ Keyi Coll Shaoxing 312369 Peoples R China Zhejiang Sci Tech Univ Sch Sci Hangzhou 310018 Peoples R China

Accurate and fast recognition of vehicle license plates from natural scene images is a crucial and challenging task. Existing methods can recognize license plates in simple scenarios, but their performance degrades significantly in complex environments. A novel license plate detection and recognition model YOLOv5-PDLPR is proposed, which employs YOLOv5 target detection algorithm in the license plate detection part and uses the PDLPR algorithm proposed in this paper in the license plate recognition part. The PDLPR algorithm is mainly designed as follows: (1) A Multi-Head Attention mechanism is used to accurately recognize individual characters. (2) A global feature extractor network is designed to improve the completeness of the network for feature extraction. (3) The latest parallel decoder architecture is adopted to improve the inference efficiency. The experimental results show that the proposed algorithm has better accuracy and speed than the comparison algorithms, can achieve real-time recognition, and has high efficiency and robustness in complex scenes.

关键词： license plate recognition multi-head attention global feature extractor network parallel decoder YOLOv5

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parallel Decodable Two-Level Unequal Burst Error Correcting Codes

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IEEE TRANSACTIONS ON COMPUTERS 2015年第10期64卷 2902-2911页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

Approximate (or inexact) computing is an attractive paradigm for digital processing at nanometric scales for applications in which imprecision in computation can be tolerated for improvements in other computational figures of merit, such as power consumption, circuit complexity and delay. The same principles of approximate computing are investigated in this manuscript for storage protection using an unequal protection code (UEP). In the proposed UEP code, the codeword is divided into two partitions;these partitions have different error protection functions. This paper presents a new class of two-level burst error correcting UEP codes and its parallel decoder. The proposed code is more efficient than an existing code in term of code rate, area and power consumption for the parallel decoder.

关键词： Error correcting code (ECC) unequal error protection (UEP) code burst error correction parallel decoder

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DD-Net: Dual decoder Network With Curriculum Learning for Full Waveform Inversion

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IEEE TRANSACTIONS ON GEOSCIENCE AND REMOTE SENSING 2024年 62卷 1页

作者： Zhang, Xing-Yi Min, Fan Pan, Shulin Xu, Qiong Min, Xue-Yang Song, Guojie Wang, Ke Southwest Petr Univ Sch Comp Sci & Software Engn Chengdu 610500 Peoples R China Southwest Petr Univ Lab Machine Learning Chengdu 610500 Peoples R China Southwest Petr Univ Inst Artificial Intelligence Chengdu 610500 Peoples R China Southwest Petr Univ Sch Earth Sci & Technol Chengdu 610500 Peoples R China Univ Elect Sci & Technol China Sch Math Sci Chengdu 611731 Peoples R China Southwest Petr Univ Sch Sci Chengdu 610500 Peoples R China Sichuan Egretech Technol Co Ltd Chengdu 610041 Peoples R China

Deep learning full waveform inversion (DL-FWI) is gaining much research interest due to its high prediction efficiency, effective exploitation of spatial correlation, and lack of the need for an initial estimate. As a data-driven approach, it has several key issues. For example, effective deep networks need to be designed, the training process needs to be controlled, and the generalization ability needs to be enhanced. In this article, we propose a dual decoder network (DD-Net) with curriculum learning to handle these issues. First, we design a U-Net with two decoders to grasp the velocity value and stratigraphic boundary information of the velocity model. These decoders' feedback will be combined at the encoder to enhance the encoding of edge spatial information. Second, we introduce curriculum learning to network training by organizing data in three difficulty levels. The easy-to-hard training process enhances the data fitting of the network. Third, we apply the network to low-resolution seismic observations via a prenetwork dimension reducer. This can serve as a general design idea without destroying the original network characteristics. Experiments are undertaken on SEG salt datasets and four synthetic datasets from OpenFWI. The results show that our network is superior to other state-of-the-art data-driven networks.

关键词： Full waveform inversion neural network parallel decoder seismic images

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A Novel Scheme for Concurrent Error Detection of OLS parallel decoders 26th

A Novel Scheme for Concurrent Error Detection of OLS Paralle...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

作者： Kazuteru Namba Fabrizio Lombardi Graduate School of Advanced Integration Science Chiba University Department of Electrical and Computer Engineering Northeastern University

ISBN: (纸本)9781479915842

This paper presents a concurrent error detection (CED) scheme for Orthogonal Latin Square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secure (SFS) for single stuck-at faults. Extensive simulation results are also provided;different figures of merit such as area, power dissipation, gate depth and coverage are assessed. It is shown that the proposed decoder designs for (n,k) t-bit error correcting OLS codes (k=16…256;t=2…5) have modest overheads. However, the most significant advantage of the proposed scheme is that it achieves 100 % fault coverage for the whole CED circuit, thus providing a very efficient and fully fault tolerant implementation.

关键词： Error correcting code (ECC) Concurrent error detection (CED) Strongly fault secure (SFS) Orthogonal Latin square (OLS) codes parallel decoder

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Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems

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IEEE TRANSACTIONS ON COMPUTERS 2016年第6期65卷 2005-2009页

作者： Namba, Kazuteru Lombardi, Fabrizio Chiba Univ Grad Sch Adv Integrat Sci Chiba Japan Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This manuscript proposes three classes of codes for error correction in a storage system in which the memory cells do not have the same number of levels, i.e., a multiscale storage. The proposed codes are single multiscale-symbol error correction (SMSEC) codes and are capable of correcting any errors occurring on a single memory cell, namely a column-deleted SMSEC code, an element-compacted SMSEC code and a product SMSEC code. In the proposed codes, the codewords are divided into two partitions, the elements on the first partition are over GF(2(b1)), while those on the remaining partition are over GF(2(b2)). This paper also gives guidelines for selection among the three SMSEC codes to meet the desired hardware overhead in the parallel decoder for realistic parameters of the partition pair, such as (b(1), b(2)) = (4,3), (4,2) and (3,2). Moreover it is shown that the best choice for a MSS system is the SMSEC code with the shortest check bit length;if the check bit lengths of at least two codes are equal, then the use of the element-compacted SMSEC code incurs in the smallest hardware overhead.

关键词： Error correcting code (ECC) multi-scale storage system single multi-scale symbol error correcting (SMSEC) code parallel decoder

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Lossless Data Compression for Improving the Performance of a GPU-Based Beamformer

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ULTRASONIC IMAGING 2015年第2期37卷 135-151页

作者： Lok, U-Wai Fan, Gang-Wei Li, Pai-Chi Natl Taiwan Univ Grad Inst Biomed Elect & Bioinformat Taipei 10764 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10764 Taiwan

The powerful parallel computation ability of a graphics processing unit (GPU) makes it feasible to perform dynamic receive beamforming However, a real time GPU-based beamformer requires high data rate to transfer radio-frequency (RF) data from hardware to software memory, as well as from central processing unit (CPU) to GPU memory. There are data compression methods (e.g. Joint Photographic Experts Group (JPEG)) available for the hardware front end to reduce data size, alleviating the data transfer requirement of the hardware interface. Nevertheless, the required decoding time may even be larger than the transmission time of its original data, in turn degrading the overall performance of the GPU-based beamformer. This article proposes and implements a lossless compression-decompression algorithm, which enables in parallel compression and decompression of data. By this means, the data transfer requirement of hardware interface and the transmission time of CPU to GPU data transfers are reduced, without sacrificing image quality. In simulation results, the compression ratio reached around 1.7. The encoder design of our lossless compression approach requires low hardware resources and reasonable latency in a field programmable gate array. In addition, the transmission time of transferring data from CPU to GPU with the parallel decoding process improved by threefold, as compared with transferring original uncompressed data. These results show that our proposed lossless compression plus parallel decoder approach not only mitigate the transmission bandwidth requirement to transfer data from hardware front end to software system but also reduce the transmission time for CPU to GPU data transfer.

关键词： beamformer compression parallel decoder GPU parallel programming

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Ultra-Low-Latency parallel SC Polar Decoding Architecture for 5G Wireless Communications

Ultra-Low-Latency Parallel SC Polar Decoding Architecture fo...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Kam, Dongyun Lee, Youngjoo Pohang Univ Sci & Technol Dept Elect Engn Pohang South Korea

ISBN: (纸本)9781728103976

In this paper, we newly present a novel parallel polar decoding architecture that significantly reduces the processing latency for 5G wireless communications. Based on the original decoding tree, the proposed scheme first constructs the small trees that generate multiple soft-decision messages in parallel, potentially reducing the decoding latency compared to the previous serialized schemes. The hard-decision estimates are then calculated at the following merging step to decide the decoded outputs and to update the parallel trees. For each parallel tree, the parallel pruning scheme is newly utilized to further optimize the processing latency. In addition, we introduce an efficient parallel decoder architecture, successfully supporting the proposed low-latency algorithm. Implementation results show that the proposed 8-parallel polar decoder in 65nm CMOS uses only 267ns to decode a (1024, 512) polar codeword of 5G system, which is 1.67 times faster than the state-of-the-art design.

关键词： Polar codes successive-cancellation decoding parallel decoder low-latency processing 5G communications

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FPGA Implementation of BCH decoder for Memory Systems 1

FPGA Implementation of BCH Decoder for Memory Systems

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International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT)

作者： Chandrashekhara, B. S. Sudha, K. L. Dayananda Sagar Coll Engn Dept ECE Bangalore Karnataka India

ISBN: (纸本)9781467392235

BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to detect and correct the errors in communication system and also on-chip (computer) memory systems. This paper presents a High-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors instead of double-adjacent errors. Its operation is based on extending an existing decoder that corrects only single-bit errors in parallel and serially corrects double-adjacent errors at low speed. The proposed constructed decoder design is suitable for nanoscale memory systems, in which double-adjacent and single-bit errors occur at a higher probability compared to the multiple-bit errors. This paper also shows that the area and delay overheads incurred by the proposed scheme are significantly lower than traditional BCH decoders capable of correcting any double-bit errors in parallel.

关键词： BCH codes Double-adjacent error correction (DAEC) Error correcting code (ECC) parallel decoder Shortened BCH codes

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