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High-throughput software LDPC decoder on GPU

EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING 2024年第1期2024卷 91页

作者： Liu, Zhanxian Zhao, Ling Univ Sci & Technol Beijing Sch Comp & Commun Engn 30 Xueyuan Rd Beijing 100083 Peoples R China Beihang Univ Sch Elect & Informat Engn 37 Xueyuan Rd Beijing 100191 Peoples R China

The new or future communication systems require much higher flexibility and scalability to support diverse scenarios. In this paper, a high-throughput low-density parity-check (LDPC) decoder on graphics processing unit is presented to meet the flexible and scalable requirements. A memory-reduced forward/backward approach for the check node update is proposed. Moreover, elaborate on-chip memory allocations are conducted to improve memory bandwidth. The proposed (26112, 8448) 5G LDPC decoder on RTX4090 achieves 27.6 Gbps decoding throughput with five layered iterations, while the latency is less than 1 ms. Compared with related works, the throughput speedups obtained by the presented LDPC decoder are from 1.18x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.18\times$$\end{document} to 12.4x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$12.4\times$$\end{document}.

关键词： LDPC codes Min-sum 5G parallel decoding GPU

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A turbo coding system for high speed communications

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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS 2007年第10期6卷 3700-3711页

作者： Zheng, Yan-Xiu Su, Yu T. Natl Chiao Tung Univ Dept Commun Engn Hsinchu Taiwan

This paper presents a new turbo coding scheme for high data rate applications. It uses a special interleaver structure that is naturally suited for parallel processing and a multiple-round early stopping test involving both sign check and a CRC code. A memory (storage) management mechanism is included as a critical part of the decoder. The proposed coding scheme offers new design options and tradeoffs that are not available to conventional convolutional turbo codes (CTCs). In particular, it becomes possible for the decoder to employ an efficient inter-block collaborative decoding algorithm, passing the information obtained from stopping test proved blocks to other unproved blocks. It also becomes important to have a proper decoding schedule. The combined effect is improved performance and reduction in the average decoding latency. We show that the memory manager has a modular-like effect in that additional memory units render enhanced performance due not only to less forced early stopping but to possible increases of the interleaving depth. It also provides additional design tradeoff amongst performance, speed and required memory size. Depending on the decoding schedule, the degree of parallelism and other decoding resources available, the proposed scheme admits a variety of decoder architectures that meet a large range of speed and performance demands.

关键词： turbo codes interleaver inter-block permutation parallel decoding early-stopping

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High performance, high throughput turbo/SOVA decoder design

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IEEE TRANSACTIONS ON COMMUNICATIONS 2003年第4期51卷 570-579页

作者： Wang, ZF Parhi, KK Natl Semicond Corp Longmont CO 80501 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

In this pacer, two efficient approaches are proposed to improve the performance of soft-output Viterbi algorithm (SOVA)-based turbo decoders. In the first approach, an easily obtainable variable and a simple mapping function are used to compute a target scaling factor to normalize the extrinsic information output from turbo decoders. An extra coding gain of 0.5 dB can be obtained with additive white Gaussian noise channels. This approach does not introduce extra latency and the hardware overhead is negligible. In the second approach, an adaptive upper bound based on the channel reliability is set for computing the metric difference between competing paths. By combining the two approaches, we show that the new SOVA-based turbo decoders can approach maximum a posteriori probability (MAP)-based turbo decoders within 0.1 dB when the target bit-error rate (BER) is moderately low (e.g., BER < 10(-4) for 1/2 rate codes). Following this, practical implementation issues are discussed and finite precision simulation results are provided. An area-efficient parallel decoding architecture is presented in this paper as an effective approach to design high-throughput turbo/SOVA decoders. With the efficient parallel architecture, multiple times throughput of a, conventional serial decoder can be obtained by increasing the overall hardware by a small percentage. To resolve the problem of multiple memory accesses per cycle for the efficient parallel architecture, a novel two-level hierarchical interleaver architecture is proposed. Simulation results show that the, proposed interleaver architecture performs as well as random interleavers, while requiring much less storage of random patterns.

关键词： high performance high throughput low power parallel decoding soft-output Viterbi algorithm (SOVA) decoder turbo codes turbo interleaver

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High-Throughput Multi-Codeword Decoder for Non-Binary LDPC Codes on GPU

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IEEE COMMUNICATIONS LETTERS 2018年第3期22卷 486-489页

作者： Liu, Zhanxian Liu, Rongke Hou, Yi Zhao, Ling Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China

This letter presents a graphics processing unit (GPU)-based non-binary low density parity check multi-codeword decoder with both kernel execution and data transfer optimizations. A novel multi-codeword data structure and its corresponding parallelism are proposed to boost the compute unified device architecture kernel execution. Moreover, practical methods of hiding the data transfer latency are presented to improve data transfer efficiency. Experimental results demonstrate that the throughput speedups achieved by the proposed decoder range from 3.12x to 185x over various Galois fields compared with the existing works on GPU.

关键词： Non-binary LDPC CUDA multi-codeword parallel decoding GPU

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Efficient encoding and decoding schemes for balanced codes

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IEEE TRANSACTIONS ON COMPUTERS 2003年第9期52卷 1229-1232页

作者： Youn, JH Bose, B Univ Nebraska Dept Comp Sci Omaha NE 68182 USA Oregon State Univ Sch Elect Engn & Comp Sci Corvallis OR 97331 USA

In this paper, we introduce two encoding and decoding methods for balanced codes. The proposed methods are more efficient in terms of computational complexity. The first one complements several appropriate bits at a time instead of complementing one bit at a time as done in Knuth's method. The second one is a parallel implementation of Knuth's method.

关键词： balanced codes parallel encoding parallel decoding

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Exploiting Subcarrier Redundancy for Concurrent OFDM Backscatter Communication

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IEEE WIRELESS COMMUNICATIONS LETTERS 2023年第5期12卷 828-832页

作者： Peng, Yuxiang Zhang, Yu Xiao, Lixia Zeng, Yong Jiang, Tao Huazhong Univ Sci & Technol Res Ctr 6G Mobile Commun Sch Cyber Sci & Engn Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Peoples R China Purple Mt Labs Pervas Commun Res Ctr Nanjing 211111 Peoples R China

This letter proposes an OFDM backscatter system that supports multi-tag concurrent transmission to improve spectral efficiency. Our key insight is that a single subcarrier in OFDM signals is sufficient to decode the backscatter data of a single tag that employs OFDM symbol-level modulation, leaving dozens of subcarriers underutilized and redundant. Hence, by exploring the equivalent channel that contains the cascaded backscatter channel and the tag data, we exploit the subcarrier redundancy for multi-tag parallel decoding. Moreover, we propose a low-overhead estimation scheme for the equivalent channel. Experimental results show that our proposed design successfully realizes 4-tag concurrent backscatter transmission over a range of 21 m.

关键词： Backscatter OFDM Symbols Channel estimation Transmitters Termination of employment Estimation Backscatter communication concurrent transmission parallel decoding

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Periodic Pattern Coding for Last Level Cache Data Compression

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2013年第12期E96A卷 2351-2359页

作者： Kaneko, Haruhiko Tokyo Inst Technol Dept Comp Sci Tokyo 1528552 Japan

In spite of continuous improvement of computational power of multi/many-core processors, the memory access performance of the processors has not been improved sufficiently, and thus the overall performance of recent processors is often restricted by the delay of off-chip memory accesses. Low-delay data compression for last level cache (LLC) would be effective to improve the processor performance because the compression increases the effective size of LLC, and thus reduces the number of off-chip memory accesses. This paper proposes a novel data compression method suitable for high-speed parallel decoding in the LLC. Since cache line data often have periodicity of certain lengths, such as 32- or 64-bit instructions, 32-bit integers, and 64-bit floating point numbers, an information word is encoded as a base pattern and a differential pattern between the original word and the base pattern. Evaluation using a GPU simulator shows that the compression ratio of the proposed coding is comparable to LZSS coding and X-Match Pro and superior to other conventional compression algorithms for cache memories. Also this paper presents an experimental decoder designed for ASIC, and the synthesized result shows that the decoder can decompress cache line data of length 32 bytes in four clock cycles. Evaluation of the IPC on the GPU simulator shows that, for several benchmark programs, the IPC achieved by the proposed coding is higher than that by the conventional B Delta I coding, where the maximum improvement of the IPC is 20%.

关键词： cache memory compression parallel decoding GPGPU de-compression delay

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Systolic array architecture implementing Berlekamp-Massey-Sakata algorithm for decoding codes on a class of algebraic curves

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IEEE TRANSACTIONS ON INFORMATION THEORY 2005年第11期51卷 3856-3871页

作者： Matsui, H Sakata, SJ Kurihara, M Mita, S Toyota Technol Inst Dept Elect & Informat Sci Tenpaku Ku Nagoya Aichi 4688511 Japan Univ Electrocommun Dept Informat & Commun Engn Chofu Tokyo 1828585 Japan

We construct a two-dimensional systolic array implementing the Berlekamp-Massey-Sakata (BMS) algorithm to provide error-locator polynomials for codes on selected algebraic curves. This array is constructed by introducing some new polynomials in order to increase the parallelism of the algorithm. The introduced polynomials are used in the majority logic scheme by Sakata et al. to correct errors up to the designed minimum distance without affecting its high speed. The arrangement of the nearest local connection of processing units in the systolic array is obtained for the general case. Furthermore, shortened systolic arrays that reduce the circuit scale and have the same function are constructed with only a slight modification of the connections and controls;this enables the adjustment of the circuit scale for different types of systems.

关键词： Berlekamp-Massey-Sakata (BMS) algorithm codes on algebraic curves Grobner basis parallel decoding systolic array

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A Multimode Area-Efficient SCL Polar Decoder

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2016年第12期24卷 3499-3512页

作者： Xiong, Chenrong Lin, Jun Yan, Zhiyuan Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA Lehigh Univ Bethlehem PA 18015 USA Nanjing Univ Sch Elect Sci & Engn Nanjing 210046 Jiangsu Peoples R China

Polar codes are of great interest, since they are the first provably capacity-achieving forward error correction codes. To improve throughput and to reduce decoding latency of polar decoders, maximum likelihood (ML) decoding units are used by successive cancellation list (SCL) decoders as well as SC decoders. This paper proposes an approximate ML (AML) decoding unit for SCL decoders first. In particular, we investigate the distribution of frozen bits of polar codes designed for both the binary erasure and additive white Gaussian noise channels, and take advantage of the distribution to reduce the complexity of the AML decoding unit, improving the throughput-area efficiency of the SCL decoders. Furthermore, a multimode (MM) SCL decoder with variable list sizes and parallelism is proposed. If high throughput or small latency is required, the decoder decodes multiple received words in parallel with a small list size. However, if error performance is of higher priority, the MM-SCL decoder switches to a serial mode with a bigger list size. Therefore, the MM-SCL decoder provides a flexible tradeoff between latency, throughput, and error performance at the expense of small overhead. Hardware implementation and synthesis results show that our polar decoders not only have a better throughput-area efficiency but also easily adapt to different communication channels and applications.

关键词： Error control codes maximum likelihood (ML) decoding multimode (MM) decoding parallel decoding polar codes successive cancellation list (SCL) decoding

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Improving the redundancy of Knuth's balancing scheme for packet transmission systems

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2019年第4期27卷 2579-2589页

作者： Mambou, Elie Ngomseu Esenogho, Ebenezer Ferreira, Hendrik Univ Johannesburg Dept Elect & Elect Engn Auckland Pk South Africa

A simple scheme was proposed by Knuth to generate binary balanced codewords from any information word. However, this method is limited in the sense that its redundancy is twice that of the full sets of balanced codes. The gap between Knuth's algorithm's redundancy and that of the full sets of balanced codes is significantly considerable. This paper attempts to reduce that gap. Furthermore, many constructions assume that a full balancing can be performed without showing the steps. A full balancing refers to the overall balancing of the encoded information together with the prefix. We propose an efficient way to perform a full balancing scheme that does not make use of lookup tables or enumerative coding.

关键词： Balanced codes binary word parallel decoding prefix coding full balancing

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