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Balanced codes with parallel encoding and decoding

IEEE TRANSACTIONS ON COMPUTERS 1999年第8期48卷 794-814页

作者： Tallini, LG Bose, B Politecn Milan Dipartimento Tec I-20133 Milan Italy Oregon State Univ Dept Comp Sci Corvallis OR 97331 USA

A balanced code with k information bits and r check bits is a binary code of length n = k + r and cardinality 2(k) such that the number of Is in each code word is equal to right perpendicular n/2 left perpendicular. This paper describes the design of efficient balanced codes with parallel encoding and parallel decoding. In this case, since area and delay of such circuits are critical factors, another parameter is introduced in the definition of balanced code: the "number of balancing functions used in the code design," p. parallel encoding and decoding algorithms independent from the chosen balancing method are given and these can be implemented by a VLSI circuit of size O(pk) and depth O(logp). This paper also presents a new balancing method: the permutation method, which, for infinitely many values of k (such as, k = 8, 10, 20, 22, 32, 34,...) is more efficient than Knuth's complementation method. This new method results in efficient balanced codes with k information bits, k even, r = 2 right perpendicular k/12 left perpendicular + 2 check bits and p = 6 balancing functions. Further, Knuth's complementation method is generalized to obtain efficient code designs for any value of the parameters k, r, and p, provided that [GRAPHICS] where m is such that [GRAPHICS]

关键词： balanced codes constant weight codes parallel encoding parallel decoding VLSI systems

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FFT-based parallel encoding algorithm for structured LDPC codes

FFT-based parallel encoding algorithm for structured LDPC co...

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11th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM 2015)

作者： Yanan Fan Xin Meng Xiujuan Yao Yi Yan University of Chinese Academy of Sciences Beijing China National Space Science Center CAS Beijing China

ISBN: (纸本)9781510821279

Structured LDPC, such as RA, IRA, ARA, QC-LDPC etc., are some important LDPC codes, these codes usually have very good performance and facilitate the implementation of encoding and decoding for the structural features they have. A new method for the encoding of the structured LDPC codes has been presented, namely FFT-based parallel encoding algorithm, which uses FFT to realize the parallel encoding of LDPC codes by achieving the circular convolution in the frequency domain. The study shows that the proposed algorithm has lower computational complexity than the previously proposed encoding algorithm. Although transforming to the frequency domain requires complex operations in real domain which increasing the number of the quantization points, the throughput of the encoder has greatly improved because of the increase of the degree of parallelism. The simulation results show that the computational complexity of the FFT-based encoding algorithm has an approximately linear relationship with the size of sub-circulate matrix, and when this size goes larger, the newly proposed algorithm will possess a lower computational complexity and a higher throughput compared with the previously proposed algorithms.

关键词： Circular Convolution FFT-Based High Throughput Lower Computational Complexity parallel encoding Structured LDPC parallel encoding low density parity check codes complexity classes Circular Convolution Frequency-domain analysis real number field

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parallel HD encoding on CELL

Parallel HD Encoding on CELL

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IEEE International Symposium on Circuits and Systems (ISCAS 2009)

作者： He, Xun Fang, Xiangzhong Wang, Ci Goto, Satoshi Shanghai Jiao Tong Univ SEIEE Shanghai 200030 Peoples R China Waseda Univ Grad Sch IPS Kitakyushu Fukuoka 8080135 Japan

ISBN: (纸本)9781424438273

The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).

关键词： Cells Multi-core processors ENCODER HD PROCESSOR HIGH-PERFORMANCE parallel encoding parallel Lines algorithms

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A simple parallel algorithm for the Ziv-Lempel encoding

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1998年第4期E81A卷 709-712页

作者： Iwata, K Morii, M Uyematsu, T Okamoto, E Univ Tokushima Fac Engn Dept Informat Sci & Intelligent Syst Tokushima 7708506 Japan Tokyo Inst Technol Dept Elect & Elect Engn Tokyo 1528552 Japan Japan Adv Inst Sci & Technol Sch Informat Sci Hokuriku Ishikawa 9231292 Japan

Many Ziv-Lempel algorithms have a similar property, that is, slow encoding and fast decoding. This paper proposes a simple improved Ziv-Lempel algorithm to encode a large amount of data quickly as well as compactly by... 详细信息

关键词： parallel encoding sliding-window Ziv-Lempel algorithm longest-matched string universal data compression

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parallel fast inter mode decision for H.264/AVC encoding

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JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION 2013年第8期24卷 1443-1449页

作者： Chen, Jianwen Villasenor, John He, Yun Luo, Gang Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA Tsinghua Natl Lab Informat Sci & Technol Dept Elect Engn Beijing Peoples R China Harvard Univ Sch Med Schepens Eye Res Inst Boston MA USA

For H.264/AVC encoding, the mode selection process consumes a large proportion of the overall computation. To reduce this burden, various fast mode decision algorithms have been proposed. The current fast mode decision algorithms usually exploit the relationship among the coding modes and use the context-based approach to reduce the number of modes to be checked for both intra coding and inter coding. The parallel capacity of hardware architectures are also taken into consideration. However, almost all the parallel fast mode decision designs are focusing on intra coding. In this paper, a hardware friendly parallel fast inter mode decision method is proposed. With the proposed method, the inter mode decision can be conducted efficiently in one pass and significant encoding speedup can be achieved with negligible coding efficiency loss. Moreover, the proposed method can be easily mapped to hardware architecture which can be used for the real-time video encoding. (C) 2013 Elsevier Inc. All rights reserved.

关键词： Fast mode decision H.264/AVC Video codec design parallel encoding

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PARAMESH: A parallel adaptive mesh refinement community toolkit

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COMPUTER PHYSICS COMMUNICATIONS 2000年第3期126卷 330-354页

作者： MacNeice, P Olson, KM Mobarry, C de Fainchtein, R Packer, C Drexel Univ NASA Goddard Space Flight Ctr Greenbelt MD 20771 USA Univ Chicago Enrico Fermi Inst Chicago IL 60637 USA Raytheon ITSS Lanham MD 20706 USA

In this paper we describe a community toolkit which is designed to provide parallel support with adaptive mesh capability For a large and important class of computational models, those using structured, logically Cartesian meshes. The package of Fortran 90 subroutines, called PARAMESH, is designed to provide an application developer with an easy route to extend an existing serial code which uses a logically Cartesian structured mesh into a parallel code with adaptive mesh refinement. Alternatively, in its simplest use, and with minimal effort, it can operate as a domain decomposition tool for users who want to parallelize their serial codes, but who do not wish to use adaptivity. The package can provide them with an incremental evolutionary path for their code, converting it first to uniformly refined parallel code, and then later if they so desire, adding adaptivity. (C) 2000 Elsevier Science B.V. All rights reserved.

关键词： tool cases Adaptive mesh refinement application developer Codes parallel encoding parallel Lines Descartes

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parallel constrained coding with application to two-dimensional constraints

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IEEE TRANSACTIONS ON INFORMATION THEORY 2002年第5期48卷 1009-1020页

作者： Halevy, S Roth, RM Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel

A parallel constrained coding scheme is considered where p-blocks of raw data are encoded simultaneously into q tracks such that the contents of each track belong to a given constraint S. It Is shown that as q increases, there are parallel block-decodable encoders for S whose coding ratio p/q converges to the capacity of S. Examples are provided where parallel coding allows block-decodable encoders, while conventional coding, at the same rate, does not. parallel encoders are then applied as building blocks in the construction, of block-decodable encoders for certain families of two-dimensional constraints.

关键词： block-decodable encoders Kronecker product parallel encoding runlength-limited (RLL) constraints two-dimensional constraint

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Data-parallel support for numerical irregular problems

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parallel COMPUTING 1999年第13-14期25卷 1971-1994页

作者： Zapata, EL Plata, O Asenjo, R Trabado, GP Univ Malaga Dept Comp Architecture E-29080 Malaga Spain

A large class of intensive numerical applications show an irregular structure, exhibiting an unpredictable runtime behavior. Two kinds of irregularity can be distinguished in these applications. First, irregular control structures, derived from the use of conditional statements on data only known at runtime. Second, irregular data structures, derived from computations involving sparse matrices, grids, trees, graphs, etc. Many of these applications exhibit a large amount of parallelism, but the above features usually make that exploiting such parallelism becomes a very difficult task. This paper discusses the effective parallelization of numerical irregular codes, focusing on the definition and use of data-parallel extensions to express the parallelism that they exhibit. We show that the combination of data distributions with storage structures allows to obtain efficient parallel codes. Codes dealing with sparse matrices, finite element methods and molecular dynamics (MD) simulations are taken as working examples. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： Synclitism parallelism Finite element method data distribution parallel encoding Codes Memory architecture Control Architecture Runtime

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Nuclear vowel priming and anticipatory oral postures: evidence for parallel phonological planning?

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LANGUAGE COGNITION AND NEUROSCIENCE 2020年第1期35卷 106-123页

作者： Krause, Peter A. Kawamoto, Alan H. Univ Calif Santa Cruz Dept Psychol Santa Cruz CA 95064 USA

Linguistic and psycholinguistic theories of speech planning typically assume serial phonological encoding. However, under some neurally-inspired speech models, phonological elements are initially co-active in a parallel planning space. Research using acoustic reaction times has perhaps mistakenly attributed execution-level phonetic effects to serial encoding. We used motion-tracked digital video to measure lip posture. In two form-preparation experiments, participants were sometimes primed with the nuclear vowels of CVC words. All words contained either /i/ (spread lips;e.g. "seed") or /u/ (rounded lips, e.g. "soup"). The initial consonants were uncertain. Analyses emphasised oral postures preceding stimulus presentation. In Experiment 1, participants' early postures anticipated the upcoming vowel when it was primed. Experiment 2 included two pairs of vowel-primed blocks. The words of one /i/-block began with rounded consonants. Primed vowels influenced anticipatory articulation except when superseded by conflicting demands from likely initial consonants. We discuss the implications for parallel encoding.

关键词： Articulation form preparation gestural timing parallel encoding phonological priming trajectory analysis

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Towards High-Level parallel Programming Models for Multicore Systems

Towards High-Level Parallel Programming Models for Multicore...

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International Conference on Advanced Software Engineering and Its Applications

作者： Marowka, Ami Shenkar Coll Engn & Design IL-52526 Ramat Gan Israel

ISBN: (纸本)9780769534329

parallel programming represents the next turning point in how software engineers write software. Multicore processors can be found today in the heart of supercomputers, desktop computers and laptops. Consequently, applications will increasingly need to be parallelized to fully exploit multicore processors throughput gains now becoming available. Unfortunately, writing parallel code is more complex than writing serial code. This is where the Threading Building Blocks (TBB) approach enters the parallel computing picture. TBB helps developers create multithreaded applications more easily by using high-level abstractions to hide much of the complexity of parallel programming. We study the programmability and performance of TBB by evaluating several practical applications. The results show very promising performance but parallel programming with TBB is still tedious and error-prone.

关键词： parallel programming Multi-core processors level of abstraction supercomputer programmability Serial Publications parallel encoding

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