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parallel implementation of PIPO and Its Application for Format Preserving Encryption

IEEE ACCESS 2022年 10卷 99963-99972页

作者： Kim, Hyunji Kim, Hyunjun Eum, Siwoo Kwon, Hyeokdong Yang, Yujin Seo, Hwajeong Hansung Univ IT Convergence Div Seoul 02876 South Korea

The PIPO block cipher, a domestic lightweight block cipher, was announced at ICISC'20. In particular, the bitslicing technique is implemented in the S-Layer for the PIPO block cipher. Because this is a part that can be operated in parallel, we implemented the PIPO block cipher efficiently in a parallel approach through AVX2 instructions, and provide implementations for ECB and CTR modes. Compared to the existing PIPO implementation, we achieved a performance improvement by 7.345x. In addition, we applied the AVX2-PIPO implementation to the round function of format-preserving encryption. When repeatedly encrypting 128-byte plaintext, we achieved performance similar to that of the existing FF1-AES implementation. The FF1-AVX2-PIPO implementation successfully encrypted the database and enabled efficient database management in terms of memory space and speed factor. Finally, AVX2-PIPO-CTR and FF1-AVX2-PIPO were applied to image processing. In the case of CTR mode, the encryption performance was better than that of ECB mode. Partial encryption with object detection and FF1-AVX2-PIPO was successfully performed, and it is expected that privacy protection in CCTV or image processing can be improved.

关键词： PIPO block cipher parallel implementation format preserving encryption

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BlinK: Breaking parallel implementation of CRYSTALS-Kyber with Side-Channel Attack 42

BlinK: Breaking Parallel Implementation of CRYSTALS-Kyber wi...

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42nd International Conference on Computer Design

作者： Benini, Luca Swiss Fed Inst Technol Zurich Switzerland Univ Bologna Bologna Italy

ISBN: (纸本)9798350380415;9798350380408

The post-quantum key encapsulation mechanism, CRYSTALS-Kyber, has recently been selected by the National Institute of Standards and Technology (NIST) for standardization. Consequently, it becomes crucial to assess the resistance of CRYSTALS-Kyber implementations to physical attacks. While side-channel attacks on embedded software platforms have been well studied, this work introduces a novel attack on hardware implementations of CRYSTALS-Kyber. Initially, we propose a multi-ciphertext message recovery attack that is capable of extracting messages from side-channel measurements of parallel message encoding. Building upon this, we further develop a key recovery attack based on an optimal ciphertext-choosing strategy that maximizes key recovery accuracy, as well as a lattice reduction attack capable of solving the entire secret key even when confronted with an imperfect side-channel distinguisher. To evaluate the effectiveness of our attack, we conducted experiments on a Xilinx FPGA board. Our results demonstrate that our attack is capable of successfully recovering the secret key using 96 power traces, with a success rate of 100%. This study reveals that parallel implementations remain vulnerable to side-channel attacks, underscoring the necessity of additional analysis and countermeasures for lattice-based schemes implemented in parallel.

关键词： Hardware Security Post-quantum Cryptography parallel implementation Side-channel Attack Chosen-ciphertext Attack Lattice Reduction

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parallel implementation of hybrid scheme for simulation of heat flow within a Wavy Square Enclosure with line heat source filled with nanofluid under Magnetic field effect

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HEAT TRANSFER 2021年第2期50卷 1494-1522页

作者： Nishad, Surabhi Bhargava, Rama Indian Inst Technol Roorkee Dept Math Roorkee 247667 Uttarakhand India

In the present paper, the hybrid meshfree method with parallel algorithm has been implemented to simulate natural convection inside a wavy square enclosure with a line heat source placed on the right vertical wall of the cavity. The fluid is assumed to be aCu-waterbased nanofluid where single-phase model is used in two dimensions. The computations are performed for variation of the Rayleigh number, Hartmann number, positions of the heat source as well as size of the heat source. The results are shown in terms of streamlines, isotherms, and Nusselt numbers. Such problems have direct applications for effective cooling or heating of the enclosures with the heat sources.

关键词： heat source hybrid FEM EFGM nanofluid natural convection parallel implementation

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Visual predictive control for differential drive robots with parallel implementation on GPU

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COMPUTERS & ELECTRICAL ENGINEERING 2022年 102卷

作者： Durand-Petiteville, A. Cadenat, V. Fed Univ Pernambuco UFPE Dept Mech Engn Ave Arquitetura BR-50740550 Recife PE Brazil CNRS 7 Ave colonel Roche F-31400 Toulouse France Univ Toulouse UPS F-31400 Toulouse France

This work focuses on the control of a camera mounted on a differential drive robot via a VPC (Visual Predictive Control) scheme. First, an exact model of the visual feature prediction is presented for this robotic system. Next, relying on the equivalent command vector concept, a parallel implementation on a GPU (Graphics Processing Unit) of the computation of the cost function and its gradient is presented. Finally, results show that the proposed approach is more accurate than the ones classically used and can be up to six times faster than CPU-based (Central Processing Unit) one for large prediction horizons and numerous visual features. It then becomes possible to implement a VPC controller running sufficiently fast to perform a navigation tasks, while guaranteeing the closed-loop stability by relying on large prediction horizons.

关键词： Mobile robot Visual servoing Model predictive control parallel implementation

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parallel implementation of PIPO Block Cipher on 32-bit RISC-V Processor 22nd

Parallel Implementation of PIPO Block Cipher on 32-bit RISC-...

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22nd World Conference on Information Security Application (WISA)

作者： Kwak, YuJin Kim, YoungBeom Seo, Seog Chung Kookmin Univ Dept Informat Secur Cryptol & Math Seoul South Korea Kookmin Univ Dept Financial Informat Secur Seoul South Korea

ISBN: (纸本)9783030894320;9783030894313

In ICISC 2020, 64-bit PIPO lightweight block cipher was presented. The main design goals of PIPO are the implementation-friendly and the ease of designing side-channel protection techniques. Until now, the performance of PIPO has been investigated only on 8-bit AVR environment. Thus, optimization strategies on various embedded devices need to be investigated for PIPO's wide usage in various IoT applications. For filling this gap, in this paper, we present an optimized software implementation of PIPO cipher on 32-bit RISC-V processor being widely considered as an alternative embedded processor for ARM processors. For optimal performance, we propose several novel techniques: optimal register scheduling for minimizing the number of memory accesses, data parallel processing approach by using 32-bit register set, and combined internal process. In result, our software shows 128.5% improved performance on PIPO-64/128 basis than the simple ported version of RISC-V. In addition, our implementation showed 393.52% improvement over the encryption performance of the PIPO reference code, despite including the key scheduling process. As far as we know, this is the first optimal implementation of PIPO block cipher on RISC-V environment.

关键词： PIPO Optimization 32-bit RISC-V Embedded Efficient implementation parallel implementation

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parallel implementation of empirical mode decomposition for nearly bandlimited signals via polyphase representation

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SIGNAL IMAGE AND VIDEO PROCESSING 2020年第2期14卷 225-232页

作者： Ye, Qiuliang Ling, Bingo Wing-Kuen Lun, Daniel P. K. Kuang, Weichao Guangdong Univ Technol Sch Informat Engn Guangzhou Peoples R China Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Peoples R China

Nearly bandlimited signals play an important role in the biomedical signal processing community. The common method to analyze these signals is via the empirical mode decomposition approach which decomposes the non-stationary signals into the sums of the intrinsic mode functions. However, this method is computational demanding. A natural idea to reduce the computational cost is via the block processing. However, the severe boundary effect would happen due to the discontinuities between two consecutive blocks. In order to solve this problem, this paper proposes to realize the parallel implementation via polyphase representation. That is, the empirical mode decomposition is implemented on each polyphase component of the original signal. Then each sub-signals are combined after upsampling. The simulation results show that our proposed method achieves the approximate intrinsic mode functions both qualitatively and quantitatively very close to the true intrinsic mode functions. Besides, compared with the conventional block processing method which significantly suffered from the boundary effect problem, our proposed method does not have this issue.

关键词： Empirical mode decomposition Polyphase representation parallel implementation Bandlimited signals

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parallel implementation of the Non-Overlapping Template Matching Test Using CUDA

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China Communications 2020年第8期17卷 234-241页

作者： Kaikai Li Jianguo Zhang Pu Li Anbang Wang Yuncai Wang Key Lab of Advanced Transducers and Intelligent Control System(Taiyuan University of Technology) Ministry of Education&Shanxi ProvinceTaiyuan 030024China College of Information Engineering Guangdong University of TechnologyGuangzhou 510006China Guangdong Provincial Key Laboratory of Photonics Information Technology Guangdong University of TechnologyGuangzhou 510006China

NIST(National Institute of Standards and Technology) statistical test recognized as the most authoritative is widely used in verifying the randomness of binary sequences. The Non-overlapping Template Matching Test as the 7 th test of the NIST Test Suit is remarkably time consuming and the slow performance is one of the major hurdles in the testing process. In this paper, we present an efficient bit-parallel matching algorithm and segmented scan-based strategy for execution on Graphics Processing Unit(GPU) using NVIDIA Compute Unified Device Architecture(CUDA). Experimental results show the significant performance improvement of the parallelized Non-overlapping Template Matching Test, the running speed is 483 times faster than the original NIST implementation without attenuating the test result accuracy.

关键词： random numbers CUDA non-overlapping template matching test parallel implementation NIST test

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A Spark-Based parallel implementation of Compressed Hyperspectral Image Reconstruction and Anomaly Detection 10

A Spark-Based Parallel Implementation of Compressed Hyperspe...

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10th International Conference on Advanced Cloud and Big Data (CBD)

作者： Zhu, Qiliang Zhu, Yaoqin Sun, Jin Wu, Zebin Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing Peoples R China

ISBN: (纸本)9798350309713

Joint reconstruction and anomaly detection(JRAD) is an effective method for hyperspectral image reconstruction and anomaly detection that uses the tensor kernel norm to characterize the spectral-spatial correlation information, which can better separate abnormal pixels while reconstructing the image. However, with the increasing scale of remote sensing data, JRAD algorithm would suffer from large amount of computation load and high resource consumption on single-machine platforms. To address these limitations, this paper proposes a Spark-based parallel implementation for JRAD algorithm. Combining with the characteristics of hyperspectral image data represented by tensors, we propose a parallel processing flow for compressed sensing which is a major procedure in JRAD. In addition, a method for parallel iterative execution of complex tensor groups is also developed for accelerating the reconstruction and anomaly detection process on Spark. Experimental result demonstrate that, compared with the serial JRAD algorithm, the parallel JRAD implemented in this work reduces memory consumption and enhances the computational efficiency in terms of a considerable speedup on Spark. The Spark-based implementation also guarantees image reconstruction and anomaly detection accuracy and related performance metrics.

关键词： hyperspectral image reconstruction anomaly detection compressed sensing parallel implementation Spark

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parallel implementation of K-Means Algorithm on FPGA

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IEEE ACCESS 2020年 8卷 41071-41084页

作者： Dias, Leonardo A. Ferreira, Joao C. Fernandes, Marcelo A. C. Univ Fed Rio Grande do Norte Lab Machine Learning & Intelligent Instrumentat nPITI IMD BR-59078970 Natal RN Brazil Univ Porto INESC TEC P-4200465 Porto Portugal Univ Porto Fac Engn P-4200465 Porto Portugal Univ Fed Rio Grande do Norte Dept Comp Engn & Automat BR-59078970 Natal RN Brazil Harvard Univ John A Paulson Sch Engn & Appl Sci Cambridge MA 02138 USA

The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system's processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

关键词： parallel implementation FPGA K-means algorithm reconfigurable computing

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parallel implementation of a Target Detection and Tracking System on a Graphics Processing Unit 28

Parallel Implementation of a Target Detection and Tracking S...

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28th Signal Processing and Communications Applications Conference (SIU)

作者： Ataman, Ferhat Can Aksoy, Tolga ASELSAN AS Goruntu Isleme & Bilgisayark Gor Mdl Ankara Turkey

ISBN: (纸本)9781728172064

In these days, with spreading imaging systems, target detection and tracking become an important utility of the systems. In literature, detecting and tracking targets that have various different features in military or civilian applications are common research are of the community. The main purpose on target detecting is detecting objects that can be disassociated from background. They can be stationary or moving. After detecting targets, state vectors of the targets that can include position, velocity, magnitude etc. are predicted via tracking algorithm. In this paper, for detecting targets, salient region extracting is aimed so, Boolean Map Salient, (BMS), approach is used. For tracking targets, Bayesian approach based particle filter is used. Particle filter tries to find probability density function, (PDF), using particles with different weights. The main purpose of choosing particle filter is nonlinear behaviors can be represented. There are limited time for finding salient objects and tracking them in an embedded system. For this reason, to decrease processing time of the application, it is decided to use graphics processing unit, (GPU). It is observed that parallel implementation on a graphics processing unit can provide significant improvements on processing time.

关键词： detection and tracking system parallel implementation boolean map saliency particle filter

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