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THE ORACLE SPARC T5 16-CORE processor SCALES TO EIGHT SOCKETS

IEEE MICRO 2013年第2期33卷 48-57页

作者： Feehrer, John Jairath, Sumti Loewenstein, Paul Sivaramakrishnan, Ram Smentek, David Turullols, Sebastian Vahidsafa, Ali Oracle Santa Clara CA 95054 USA Oracle Hardware Santa Clara CA 95054 USA

The oracle sparc T5 processor more than doubles the throughput of the sparc T4 processor, while increasing per-thread performance, scalability, power efficiency, and I/O bandwidth. the authors detail the improvements ... 详细信息

关键词： Cache storage Computer architecture Fault tolerance Memory Multicore processing Multiprocessors Power system management Program processors Oracle Sparc T4 Sparc T5 availability cache memory computer architecture computer performance directory cache coherence encryption fault tolerance microprocessors multicore processing multiprocessor interconnection multiprocessor scaling multithreaded processors parallel architectures power management processor architectures reliability parallel processor interconnection Fault tolerance Cache memory Multiprocessor Memory macroprocessor cache storage processor Architectures Computer Architecture COMPUTER PERFORMANCE cryptography Program processors Power system management parallel architectures Information retrieval systems-Teletext and videotex

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Low Overhead Message Passing for High Performance Many-Core processors

Low Overhead Message Passing for High Performance Many-Core ...

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1st International Symposium on Computing and Networking (CANDAR)

作者： Kumar, Sumeet S. Djie, Mitzi Tjin A. van Leuken, Rene Delft Univ Technol Circuits & Syst Grp Fac EEMCS NL-2600 AA Delft Netherlands

ISBN: (纸本)9781479927951

Many-core processors provide the raw computation power required by modern high-performance multimedia and signal processing workloads. The translation of this into execution performance is often constrained by the overheads of communication between concurrent tasks. This paper presents Pronto, a low overhead message passing system which simplifies the semantics of data movement between communicating tasks by performing buffer management, message synchronization and address translation directly in hardware. The integration of these functions into hardware results in transfer latencies upto 30% shorter than state of the art MPI derivatives. The overheads for communication in a 16-core processor array are under 5% for 64-word burst transfers with Pronto using workloads such as the JPEG decoder and FIR filter. Furthermore, this paper also studies the effect of task mapping and interconnect traffic on the predictability of data block arrival times, and illustrates a method to reduce variations.

关键词： dataflow computing message passing multicore processing multiprocessor interconnection message passing parallel processor interconnection processor Workload address translation Communication Research

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Visualizing the Five-dimensional Torus Network of the IBM Blue Gene/Q 1

Visualizing the Five-dimensional Torus Network of the IBM Bl...

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1st Workshop on Visual Performance Analysis (VPA)

作者： McCarthy, Collin M. Isaacs, Katherine E. Bhatele, Abhinav Bremer, Peer-Timo Hamann, Bernd Univ Calif Davis Dept Comp Sci Davis CA 95616 USA Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781479970582

Understanding the interactions between a parallel application and the interconnection network over which it exchanges data is critical to optimizing performance in modern supercomputers. However, recent supercomputing architectures use networks that do not have natural low-dimensional representations, making them difficult to comprehend or visualize. In particular, high-dimensional torus networks are common and are used in four of the top ten supercomputers and eight of the top ten on the Graph500 list. We present a new visualization of five-dimensional torus networks. We use four connected views depicting the network at different levels of detail, allowing analysts to observe general large-scale traffic patterns while simultaneously viewing individual links or outliers in any specific section of the network. We demonstrate this approach by analyzing network traffic for a pF3D simulation running on the IBM Blue Gene/Q architecture, and show how it is both intuitive and effective for understanding and optimizing parallel application behavior.

关键词： IBM computers computer architecture data visualisation parallel machines IBM Blue Gene/Q IBM Blue Gene/Q architecture data exchanges five-dimensional torus network visualization general large-scale traffic patterns high-dimensional torus networks interconnection network pF3D simulation supercomputing architectures Context Data visualization Measurement Multiprocessor interconnection Supercomputers Three-dimensional displays Data visualisation supercomputer interconnection networks IBM computers three-dimensional displays data exchange Computer Architecture parallel machines parallel processor interconnection toruses Torus traffic network

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Large-Scale interconnection Network Simulation Methods Based on Cellular Automata 5

Large-Scale Interconnection Network Simulation Methods Based...

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5th International Symposium on Computing and Networking (CANDAR)

作者： Yokota, Takashi Ootsu, Kanemitsu Ohkawa, Takeshi Utsunomiya Univ Grad Sch Engn Dept Informat Syst Sci 7-1-2 Yoto Utsunomiya Tochigi 3218585 Japan

ISBN: (纸本)9781538620878

interconnection network (ICN) has been playing an important role in parallel systems, since it greatly affects the system-level organization as well as its inherent communication capability. State-of-the-art parallel systems employ a huge number of computing nodes that are connected by an interconnection network. In general, an interconnection network shows nonlinear phenomena in its communication performance, most of them are caused by congestion. Thus, designing a large-scale parallel system requires sufficient discussions through repetitive simulation runs. This causes another problem in simulating a large-scale system within a reasonable cost. We have introduced the cellular automata principle in the ICN simulation and proposed an effective simulation model as a promising solution. However, the proposed method is insufficient in packet length and memory usage. This paper extends our prior simulation model to solve the problems. We firstly extend the existing cellular automata based model to match multiple-length packets. Furthermore, we discuss reduction methods of memory resources and propose a compressed buffer model and composite packet information. The proposed models have a good affinity to GPGPU technology and the GPU-based simulator accelerates simulation upto about 364 times from sequential execution on a single CPU. Furthermore, since the proposed models are applicable in the shared memory model, multithread implementation of the proposed methods achieve about 78 times speed-ups at the maximum.

关键词： Automata Computational modeling Acceleration Field programmable gate arrays Multiprocessor interconnection Organizations Program processors Field programmable gate arrays interconnection networks Program processors Automata Cellular automata Computational modeling parallel system acceleration parallel processor interconnection Simulation models sequential carry simulating Organizations packet length

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RAM-Based Micro-Architecture for a High-Throughput interconnection Network 36

RAM-Based Micro-Architecture for a High-Throughput Interconn...

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36th IEEE Sarnoff Symposium

作者： Suvakovic, Dusan van Wijngaarden, Adriaan J. Alcatel Lucent Bell Labs 600 Mt Ave Murray Hill NJ USA

ISBN: (纸本)9781467380423

A novel micro-architecture of an interconnection network is proposed which realizes a strictly non-blocking switch operation in three stages by employing word-wise circular-shift circuits and a number of small banks of dual-port (DP) static random access memory (SRAM). The interconnection network is controlled by a single, centralized controller, which distributes the words across the DP SRAM banks in a predefined fashion and uses a single configurable circular-shift circuit to apply the switch operation for a given input-output mapping. The proposed micro-architecture is strictly non-blocking and has a low, fixed-valued input-output latency. Its operation does not require traffic segmentation into uniformly-sized cells. Our analysis also indicates that this architecture is compact and energy-efficient when implemented in CMOS. The proposed architecture is suitable for a wide range of applications, from switch fabric in network switches and routers to computer interconnection networks and networks-on-a-chip.

关键词： CMOS integrated circuits SRAM chips multiprocessor interconnection networks network-on-chip CMOS integrated circuit DP SRAM banks RAM-based microarchitecture computer interconnection networks dual-port static random access memory high-throughput interconnection network input-output mapping network routers network switches networks-on-a-chip nonblocking switch operation single centralized controller single configurable circular-shift circuit switch fabric word-wise circular-shift circuits Fabrics Multiprocessor interconnection Ports (Computers) Random access memory Switches Switching circuits CMOS integrated circuits interconnection networks Static random access storage switch fabric multiprocessor interconnection networks network router Switches Switched circuits random access machine network-on-chip Textile fabrics fabric Network switching parallel processor interconnection INPUT-OUTPUT

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Performance of the Achilles Router

Performance of the Achilles Router

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8th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2003)

作者： Tham, S Morris, J Univ Western Australia Sch Elect Elect & Comp Engn Nedlands WA 6009 Australia

ISBN: (纸本)354020122X

The Achilles Router provides low latency, high bandwidth connections between processors, enabling a network of low-cost processors to perform as a high-performance parallel processor. It is also economical, being constructed from low cost Field Programmable Gate Arrays (FPGAs). These programmable devices allow it to be re-programmed for use in a variety of network topologies;they also permit 'tuning' the router for optimum performance in different applications. A key factor in its simplicity and performance is the 3-D structure: this allows us to build a full cross-bar switch with a wide, high-bandwidth datapath. The simple cross-bar circuit also has very low latency: we measured latencies of similar to800ns in the hardware and 2.5mus when software overheads were included. We measured the basic performance of an inter-processor link using Achilles, and then, using a range of benchmarks with different characteristics, showed that Achilles clearly outperforms Fast Ethernet.

关键词： parallel processor interconnection networks of workstations cross-bar switching

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Super Connectivity of Component-Composition Networks

Super Connectivity of Component-Composition Networks

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International Conference on Applied Computing and Information Technology/International Conference on Computational Science and Intelligence (ACIT-CSI)

作者： Ming-Chien Yang Department of Information Application Aletheia University Tainan Taiwan

ISBN: (纸本)9781467396431

The reliability of an interconnection network is an important issue for multiprocessor systems. The super connectivity is a novel measure for the reliability of an interconnection network. Given a graph G, the super connectivity of G is the minimum cardinality of vertices whose removal results in a disconnected graph that contains no isolated vertex. This paper studies the super connectivity of component-composition networks, which includes burnt pancake graphs, star graphs, bubble-sort graphs, pancake graphs, hypercube-like graphs, and so on. We also apply the obtained result for the component composition networks to determine the super connectivity of various known networks. For instance, we determine that the super connectivity of the n-dimensional burnt pancake graph BP n is 2n - 2 for n ≥ 2.

关键词： graph theory multiprocessing systems multiprocessor interconnection networks bubble-sort graphs burnt pancake graphs component-composition networks disconnected graph hypercube-like graphs interconnection network reliability multiprocessor systems star graphs Artificial intelligence Joining processes Multiprocessing systems Multiprocessor interconnection Program processors Reliability Scientific computing component composition networks fault-tolerance interconnection networks reliability super connectivity Multiprocessing systems interconnection networks multiprocessor interconnection networks Program processors Scientific computing Fault tolerance Graph theory Artificial Intelligence parallel processor interconnection

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Case Study on Design and Evaluation of a Multi-Soft-Core processor

Case Study on Design and Evaluation of a Multi-Soft-Core Pro...

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International Conference and Workshop on Computing and Communication (IEMCON)

作者： Michael Kirchhoff Lothar Wagner Bernd Däne Detlef Streitferdt Wolfgang Fengler Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany Group for Software Systems and Process Informatics Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781728125312

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. The trend for soft-core processors, as well as mainstream CPUs (central processing units), leads to multi-core architectures. Both the necessary memory architectures and the compilers play an important role in this process. In this paper, a novel method that aims at minimizing the necessary memory resources on the FPGA while maximizing the processing speed of any given algorithm is described. In the first step, an application-specializable multi-soft-core processor architecture is presented that is capable of solving problems while adhering to hard real-time deadlines. Its special architecture and other necessary features are discussed. Furthermore, a method for the generation of optimized machine code for each processor core as well as hard real-time compatible deadlock handling mechanisms are presented. Selected algorithms are implemented to demonstrate the functionality and efficiency of the realized approach for different configurations of the multi-soft-core processor architecture.

关键词： Microprocessors Multicore processing Memory architecture Multiprocessor interconnection Field programmable gate arrays Field programmable gate arrays Memory architecture macroprocessor parallel processor interconnection processor soft-core processor Core embedded system development processor Architectures Mechanical Code central processing units hard real-time

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